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PDF GPM6P1065A Data sheet ( Hoja de datos )

Número de pieza GPM6P1065A
Descripción 44/28/24-Pin Learning Remote Controller
Fabricantes Generalplus 
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No Preview Available ! GPM6P1065A Hoja de datos, Descripción, Manual

GPM6P1129A
GPM6P1065A
GPM6P1033A
44/28/24-Pin Learning Remote
Controller with 128/64/32KB OTP
Preliminary
OCT. 29, 2010
Version 0.4
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.

1 page




GPM6P1065A pdf
Preliminary
GPM6P1129A / GPM6P1065A / GPM6P1033A
Key Wake up
Key change wake-up from SLEEP mode
IR
Built-in IR TX can drive IR LED with up to 300mA driving
capability @ VBAT=3.0V & VLED=3.0V.
Built-in IR RX can supply capture function with sensitivity
adjustable. (2uA, 5uA, 8uA, 11uA)
Table 2-1 GPM6P1129A/1065A/1033A Configuration
Part NO.
ROM Voltage Speed ROM
Type (V) (HMz) (Byte)
GPM6P1129A OTP 2.4~3.6 8/4 128K
GPM6P1065A OTP 2.4~3.6 8/4
64K
GPM6P1033A OTP 2.4~3.6 8/4
32K
RAM
(Byte)
256
192
192
IR Tx/Rx
Tx/Rx
Tx/Rx
Tx/Rx
CCP
CAP CNT PWM
111
111
111
CPU OSC.
IO No.
INT XTAL
  26
  20
  18
PKG
LQFP44
SOP28
SOP24
3. BLOCK DIAGRAM
XTI/PD1
XTO/PD0
VBAT
VDD
VSS
RESET
OSC
circuit
Power
saving
controller
Low Voltage Reset
& Battery Sensor
RESET Management
Watch-Dog Timer
8-bit Micro-processor
(CPU)
128K/64K/32K-byte
ROM
12 bit Timer-A
PWM & Capture
controller
IR
12 bit Timer-B
Interrupt Management
128-byte RAM
PORT D[3:2]
PORT C[7:0]
PORT B[7:0]
PORT A[5:0]
Notes:
1. GPM6P1129A IOs è PA[5:0] + PB[7:0] + PC[7:0] + PD[3:0]
2. GPM6P1065A IOs è PA[5:0] + PB[7:0] + PC[3:0] + PD[1:0]
3. GPM6P1033A IOs è PA[5:0] + PB[7:0] + PC[3] + PC[0] + PD[1:0]
Figure 3-1 Block Diagram of GPM6P1129A/1065A/1033A
LED
TX/RX
PD[3:2]
PC[7:0]
PB[7:0]
PA[5:0]
© Generalplus Technology Inc.
Proprietary & Confidential
5
Oct. 29, 2010
Preliminary Version: 04

5 Page





GPM6P1065A arduino
Preliminary
GPM6P1129A / GPM6P1065A / GPM6P1033A
5.2. Memory Organization
5.2.1. Introduction
GPM6P1129A/1065A/1033A has separated address spaces for
program memory and data memory. Program memory can be
read only. GPM6P1129A contains up to 128K bytes of program
memory. Data memory that contains 256 bytes of RAM including
stack area can be read and written. GPM6P1065A contains up to
64K bytes of program memory. Data memory that contains 192
bytes of RAM including stack area can be read and written.
GPM6P1033A contains up to 32K bytes of program memory.
Data memory that contains 192 bytes of RAM including stack area
can be read and written.
5.2.2. Memory Space
Memory address allocations on the GPM6P1129A/1065A/1033A
are divided into several parts. The first 128 addresses are
allocated for special function registers, including function control
registers and I/O control registers, which allow programmer to use
the first page instruction in setting this register and help for
program size reduction.
MEMORY MAPPING:
CPU view
$0000~$007F
IO & Reg
$0080~$00FF
RAM
RAM view
RAM
$00~$7F
RAM $80~$FF
$0100~$017F
reserved
$0180~$01FF
RAM
$0200~$3FFF
reserved
$4000~$7FFF
$8000~$BFFF
$C000~$C7FF
$C800~$FFFF
ROM
(BANK)L
ROM
(BANK)H
Test Code
ROM
4
0L
ROM view
0H
0 0L
1H
1
1L
2H
2
2L
3H
3
3L
$00000~$03FFF
$04000~$07FFF
$08000~$0BFFF
$0C000~$0FFFF
$10000~$13FFF
$14000~$17FFF
$18000~$1BFFF
$1C000~$1FFFF
Bank Address: $0
$C000-$FFFF always mapping into 0L
Figure 5-4 GPM6P1129A Memory Map
GPM6P1129A’s RAM consists of 256 bytes (including Stack). In
CPU view, the RAM locations are from $080 through $FF and from
$180 to $1FF. They are mapped to RAM $000~$07F and
$080~$0FF respectively in RAM view.
GPM6P1129A supports 128K bytes of ROM. In CPU view, it has
four banks, which are BANK0~3. Each bank includes high bank
and low bank. The addresses for the four ROM banks are
located on $4000 ~ $BFFF. And the ROM area, $C000~$FFFF,
is always mapped to the LOW area $00000 ~ $1FFFF of BANK0.
MEMORY MAPPING:
CPU view
$0000~$007F
IO & Reg
$0080~$00FF
RAM
RAM view
RAM
$00~$7F
RAM $C0~$FF
$0100~$01BF
reserved
$01C0~$01FF
RAM
$0200~$3FFF
reserved
$4000~$7FFF
$8000~$BFFF
$C000~$C7FF
$C800~$FFFF
ROM
(BANK)L
ROM
(BANK)H
Test Code
ROM
2
0L
ROM view
0H
0
0L
1H
1
1L
$00000~$03FFF
$04000~$07FFF
$08000~$0BFFF
$0C000~$0FFFF
Bank Address: $0
$C000-$FFFF always mapping into 0L
Figure 5-5 GPM6P1065A Memory Map
GPM6P1065A‘s RAM consists of 192 bytes (including Stack). In
CPU view, the RAM locations are from $080 through $FF and from
$1C0 to $1FF. They are mapped to $000~$07F and $0C0~$0FF
respectively in RAM view.
GPM6P1065A supports 64K bytes of ROM. In CPU view, it has
two banks, which are BANK0~1. Each bank includes high bank
and low bank. The addresses for the two ROM banks are located
on $4000 ~ $BFFF. And the ROM area, $C000~$FFFF, is always
mapped to the LOW area $00000 to $0FFFF of BANK0.
MEMORY MAPPING:
CPU view
$0000~$007F
IO & Reg
$0080~$00FF
RAM
RAM view
RAM
$00~$7F
RAM $C0~$FF
$0100~$01BF
reserved
$01C0~$01FF
RAM
ROM view
0H
0
0L
$00000~$03FFF
$04000~$07FFF
$0200~$3FFF
reserved
$4000~$7FFF
$8000~$BFFF
$C000~$C7FF
$C800~$FFFF
ROM
(BANK)L
ROM
(BANK)H
Test Code
ROM
2
0L
Bank Address: $0
$C000-$FFFF always mapping into 0L
Figure 5-6 GPM6P1033A Memory Map
GPM6P1033A’s RAM consists of 192 bytes (including Stack). In
CPU view, the RAM locations are from $080 through $FF and from
$1C0 to $1FF. They are mapped to $000~$07F and $0C0~$0FF
respectively in RAM view.
© Generalplus Technology Inc.
Proprietary & Confidential
11
Oct. 29, 2010
Preliminary Version: 04

11 Page







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