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PDF CHL8326 Data sheet ( Hoja de datos )
| Número de pieza | CHL8326 | |
| Descripción | Digital Multi-Phase Buck Controller | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CHL8326 (archivo pdf) en la parte inferior de esta página. Total 3 Páginas | ||
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IR3536/38
Digital Multi-Phase Buck Controller CHL8326/28
FEATURES
DESCRIPTION
6-phase & 8-phase dual output PWM Controller
Phases are flexibly assigned between Loops 1 & 2
Intel® VR12, AMD® 3.4MHz SVI/PVI & Memory
modes
Overclocking & Gaming Mode with Vmax setting
Switching frequency from 200kHz to 1.2MHz per
phase
IR Efficiency Shaping Features including Variable
Gate Drive and Dynamic Phase Control
Programmable 1-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
IR Adaptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
Auto-Phase Detection with auto-compensation
Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP
I2C/SMBus/PMBus system interface for telemetry
of Temperature, Voltage, Current & Power for
both loops
Non-Volatile Memory (NVM) for custom
configuration
Compatible with IR ATL and 3.3V Tri-state Drivers
+3.3V supply voltage; -20ºC to 85ºC ambient
operation
Pb-Free, RoHS, 7x7 48-pin & 8x8 56-pin QFN, MSL2
package
APPLICATIONS
Intel ® VR12 & AMD® SVI & PVI based systems
DDR Memory with Vtt tracking
Overclocked & Gaming platforms
PIN DIAGRAM
The IR3536/CHL8326 and IR3538/CHL8328 are dual-loop
digital multi-phase buck controllers. The IR3536/CHL8326
drive up to 6 phases and the IR3538/CHL8328 drives up to
8 phases. The IR3536/CHL8326 and IR3538/CHL8328 are
fully Intel® VR12 and AMD® SVI/PVI compliant on both
loops and provide a Vtt tracking function for DDR memory.
The IR3536/CHL8326 and IR3538/CHL8328 include the
IR Efficiency Shaping Technology to deliver exceptional
efficiency at minimum cost across the entire load range.
IR Variable Gate Drive optimizes the MOSFET gate drive
voltage based on real-time load current. IR Dynamic Phase
Control adds/drops phases based upon load current.
The IR3536/CHL8326 and IR3538/CHL8328 can be
configured to enter 1-phase operation and active diode
emulation mode automatically or by command.
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors.
The I2C/PMBus interface can communicate with up to 16
IR3536/CHL8326 and IR3538/CHL8328 based VR loops.
Device configuration and fault parameters are easily
defined using the IR Intuitive Power Designer (DPDC) GUI
and stored in on-chip NVM.
The IR3536/CHL8326 and IR3538/CHL8328 provides
extensive OVP, UVP, OCP and OTP fault protection and
includes thermistor based temperature sensing with
VR_HOT signal.
NVM storage saves pins and enables a small package size.
The IR3536/CHL8326 and IR3538/CHL8328 also include
numerous features like register diagnostics for fast design
cycles and platform differentiation, truly simplifying
VRD design and enabling fastest time-to-market with its
“set-and-forget” methodology.
48 47 46 45 44 43 42 41 40 39 38 37
RCSP 1
RCSM 2
VCC 3
CFP1 /
VFIXEN_PSI2
4
VSEN 5
VRTN 6
RRES 7
TSEN 8
V18A 9
VR_READY1 /
PWRGD2
VR_READY_L21
/ PWROK2
10
11
VINSEN 12
CHL8326
48 Pin 7x7 QFN
Top View
49 GND
36 RCSP_L2
35 RCSM_L2
34 VCC
33 VSEN_L2
32 VRTN_L2
31 PWM6
30 PWM5
29 PWM4
28 PWM3
27 PWM2
26 PWM1
25 VAR_GATE
13 14 15 16 17 18 19 20 21 22 23 24
56 55 54 53 52 51 50 49 48 47 46 45 44 43
ISEN8 1
RCSP 2
RCSM 3
VCC
CFP1 /
VFIXEN_PSI2
VSEN
4
5
6
VRTN 7
RRES 8
TSEN 9
V18A 10
VR_READY1 /
PWRGD2
VR_READY_L21
/ PWROK2
11
12
GPO_B 13
VINSEN 14
CHL8328
56 Pin 8x8 QFN
Top View
57 GND
42 ISEN7
41 RCSP_L2
40 RCSM_L2
39 VCC
38 VSEN_L2
37 VRTN_L2
36 PWM8
35 PWM7
34 PWM6
33 PWM5
32 PWM4
31 PWM3
30 PWM2
29 PWM1
15 16 17 18 19 20 21 22 23 24 25 26 27 28
1Intel/MPoL mode
2AMD mode
Figure 1: IR3536/CHL8326 Package Top View
Figure 2: IR3538/CHL8328 Package Top View
1 June 21, 2013 | FINAL | V1.09
1 page | ||
| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet CHL8326.PDF ] | |
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