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PDF HDCS-2000 Data sheet ( Hoja de datos )
| Número de pieza | HDCS-2000 | |
| Descripción | CMOS Image Sensors | |
| Fabricantes | HP | |
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The HP HDCS Family of CMOS Image
Sensors
HP Part Number HDCS-2000/2100/1000/1100
Product Technical Specification
Revision 3.0
Integrated Circuits Business Division
Hewlett-Packard Company
1020 N.E. Circle Boulevard
Corvallis, Oregon 97330
Copyright (c) 1998 Hewlett Packard Co.
Data Subject to Change
1 page  
The HP HDCS Family of CMOS Image Sensors Hewlett-Packard
Table of Contents
4.2.1 Device Address Control ..........................................................................................................................70
4.2.2 Polling the STATUS register ...................................................................................................................70
4.3 Serial Synchronous Setup Example ...................................................................................................................70
4.4 Example of Changing Modes.............................................................................................................................73
4.5 UART Setup Example........................................................................................................................................74
5. Host System Interface.................................................................................................................................................79
5.1 Overview of Host System Interface ...................................................................................................................79
5.2 The HDCS sensor 44 pin package diagram .......................................................................................................80
5.3 HDCS Image Sensor Pin Description ................................................................................................................81
5.3.1 Pad Descriptions......................................................................................................................................81
5.3.1.1 Note for all PADS.....................................................................................................................81
5.3.1.2 DRDY .......................................................................................................................................82
5.3.1.3 DATA9,DATA8,DATA7,...DATA0 ........................................................................................84
5.3.1.4 IMODE .....................................................................................................................................87
5.3.1.5 TCLK ........................................................................................................................................87
5.3.1.6 TxD ...........................................................................................................................................87
5.3.1.7 RxD ...........................................................................................................................................88
5.3.1.8 nFRAME_nSYNC ....................................................................................................................88
5.3.1.9 nROW .......................................................................................................................................92
5.3.1.10 nIRQ_nCC ................................................................................................................................93
5.3.1.11 CLK...........................................................................................................................................97
5.3.1.12 nRST .........................................................................................................................................97
5.3.1.13 nSTBY ......................................................................................................................................97
5.3.1.14 VDD........................................................................................................................................97
5.3.1.15 GND........................................................................................................................................97
5.3.1.16 AVDD .....................................................................................................................................98
5.3.1.17 AGND .....................................................................................................................................98
5.3.1.18 PVDD......................................................................................................................................98
5.4 Serial Interface ...................................................................................................................................................98
5.4.1 Synchronous Serial Slave Mode..............................................................................................................98
5.4.2 Synchronous Serial Sequence Diagrams...............................................................................................105
5.4.3 Serial Interface: UART Half-Duplex Slave Mode.................................................................................108
5.4.4 UART Sequence Diagrams....................................................................................................................113
6. System Reset and Low power modes ......................................................................................................................115
6.1 System Reset ....................................................................................................................................................115
6.2 Low Power / Clock Domains. ..........................................................................................................................116
7. Packaging...................................................................................................................................................................119
7.0.1 General Package Specs..........................................................................................................................119
7.1 Package Pin List...............................................................................................................................................120
8. Electrical and Power Specifications.........................................................................................................................121
8.1 Electrical Specifications ...................................................................................................................................121
8.1.1 Absolute Maximum Ratings..................................................................................................................121
October 13, 1998
Product Technical Specification HDCS-2000/2100/1000/1100
Page 5 of 124
5 Page 
HP HDCS Family of CMOS Image Sensors Hewlett-Packard
Sensor Overview
tinues until all the pixels for the viewing window have been output on the DATA pins. The nROW status signal is asserted
when the data for the last pixel of the row has been output.
When nROW is asserted for the bottom row of the viewing window, nFRAME is also asserted.
If the CFC bit of the CONFIG register equals ‘0’, then the Sensor is in single frame mode. In single frame mode if the
nIRQ_nCC (interrupt/capture complete) status pin is enabled as capture complete, then nIRQ_nCC is asserted at the same
time as nFRAME. The RF (run flag) is turned off in the STATUS register and the sensor idles until it is told to run another
frame.
If the CFC bit of the CONFIG register equals ‘1’, then HDCS Sensor is in continuous run mode. In continuous run mode
after the assertion of nFRAME, the sensor immediately begins the next frame which has already started integrating. If
integration time is less than the time to cycle through 1 frame, then there is no delay between the processing of the bottom
row of frame X and the top row of frame X+1. If integration time is greater than the time to cycle through 1 frame, then
there is a delay between the bottom row of frame X and the top row of frame X+1. They delay equals integration time
minus the time to cycle through one frame.
Continuous Run mode is terminated by resetting the RUN bit of the CONTROL register. Single Frame mode may also be
terminated by de-asserting the RUN bit. If the SFC (stop when frame complete) bit of the CONFIG register is set when the
RUN bit is de-asserted HDCS Sensor will process until nFRAME is asserted at the normal time, then return to idle. If the
SFC (stop when frame complete) bit of the CONFIG register is not set when the RUN bit is de-asserted EYRIS/PUPIL
will immediately assert nFRAME, nROW, and nIRQ_nCC and return to the idle state. If enabled for the capture complete
function, the nIRQ_nCC (interrupt/capture complete) status flag is asserted at the same time as nFRAME for the last
frame.
October 13, 1998
Product Technical Specification HDCS-2000/2100/1000/1100
Page 11 of 124
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HDCS-2000.PDF ] | |
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