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PDF ZL40221 Data sheet ( Hoja de datos )
| Número de pieza | ZL40221 | |
| Descripción | Precision 2:6 LVDS Fanout Buffer | |
| Fabricantes | Microsemi | |
| Logotipo |  |
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Features
Inputs/Outputs
ZL40221
Precision 2:6 LVDS Fanout Buffer with Glitch-
free Input Reference Switching
and On-Chip Input Termination
Data Sheet
November 2012
Ordering Information
ZL40221LDG1 32 Pin QFN Trays
ZL40221LDF1 32 Pin QFN Tape and Reel
• Accepts two differential or single-ended inputs
• LVPECL, LVDS, CML, HCSL, LVCMOS
• Glitch-free switching of references
Matte Tin
Package size: 5 x 5 mm
-40oC to +85oC
• On-chip input termination and biasing for AC
coupled inputs
Applications
• Six precision LVDS outputs
• Operating frequency up to 750 MHz
• General purpose clock distribution
• Low jitter clock trees
Power
• Option for 2.5 V or 3.3 V power supply
• Current consumption of 97 mA
• On-chip Low Drop Out (LDO) Regulator for superior
power supply rejection
• Logic translation
• Clock and data signal restoration
• Redundant clock distribution
• Wired communications: OTN, SONET/SDH, GE,
10 GE, FC and 10G FC
• Wireless communications
Performance
• Ultra low additive jitter of 165 fs RMS
• High performance micro-processor clock
distribution
ctrl0
vt0
clk0_p
clk0_n
clk1_p
clk1_n
ctrl1
vt1
sel
Termination
and Bias
Termination
and Bias
Buffer
Figure 1 - Functional Block Diagram
1
Microsemi Corporation
Copyright 2012, Microsemi Corporation. All Rights Reserved.
out0_p
out0_n
out1_p
out1_n
out2_p
out2_n
out3_p
out3_n
out4_p
out4_n
out5_p
out5_n
1 page  
ZL40221
Data Sheet
2.0 Pin Description
Pin #
Name
Description
1, 4, clk0_p, clk0_n, Differential Input (Analog Input). Differential (or singled ended) input signals. For all
5, 8 clk1_p, clk1_n input signal configuration see Section 3.1, “Clock Inputs“.
2, 6 vt0, vt1 On-Chip Input Termination Node (Analog). Center tap between internal 50 Ohm
termination resistors.
For a DC coupled LVPECL input connect this pin through a resistor to ground; 50 Ohms
for 3.3V LVPECL or 20 Ohms for 2.5V LVPECL.
For a DC coupled LVDS input or for an AC coupled differential input, leave this pin
unconnected.
3, 7 ctrl0, ctrl1 Digital Control for On-Chip Input Termination (Input). Selects differential input mode;
0: DC coupled LVPECL or LVDS modes
1: AC coupled differential modes
These pins are internally pulled down to GND.
29, 28, out0_p, out0_n Differential Output (Analog Output). Differential outputs.
27, 26, out1_p, out1_n
22, 21, out2_p, out2_n
20, 19, out3_p, out3_n
15, 14, out4_p, out4_n
13, 12 out5_p, out5_n
11, 16,
18, 23,
25, 30
vdd Positive Supply Voltage. 2.5VDC or 3.3 VDC nominal.
9, 17,
24, 32
gnd Ground. 0 V.
31 sel Input Select (Input). Selects the reference input that is buffered;
0: clk0
1: clk1
This pin is internally pulled down to GND.
10 NC No Connection. Leave unconnected.
5
Microsemi Corporation
5 Page 
VDD_driver
CMOS
Driver
ZL40221
Zo = 50 Ohms
Data Sheet
VDD
clk_p
clk_n
Vt
NC
“1” Ctrl
Figure 12 - Clock Input - DC-coupled 3.3V CMOS
11
Microsemi Corporation
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ZL40221.PDF ] | |
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