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PDF MAX11270 Data sheet ( Hoja de datos )
| Número de pieza | MAX11270 | |
| Descripción | 64ksps Delta-Sigma ADC | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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MAX11270
EVALUATION KIT AVAILABLE
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
General Description
The MAX11270 is a 24-bit delta-sigma ADC that achieves
excellent 130dB SNR while dissipating an ultra-low 10mW.
Sample rates up to 64ksps allow both precision DC and
AC measurements. Integral nonlinearity is guaranteed
to 4ppm maximum. The THD is -122dB. The MAX11270
communicates via an SPI-compatible serial interface and
is available in a small 24-pin TSSOP package.
The MAX11270 offers a 6.5nV/√Hz noise programmable
gain amplifier with gain settings between 1x to 128x.
Optional buffers are also included to provide isolation of
the signal inputs from the switched capacitor sampling
network. This allows the MAX11270 to be used with
high-impedance sources without compromising available
dynamic range.
The MAX11270 operates from a single 2.7V to 3.6V
analog supply, or split ±1.8V analog supplies, allowing
the analog input to be sampled below ground. The digital
supply range is 2.0V to 3.6V, allowing communication with
2.5V, 3V, or 3.3V logic.
Applications
●● Scientific Instrumentation
●● High-Precision Portable Sensors
●● Medical Equipment
●● ATE
Ordering Information and Functional Diagram appear at
end of data sheet.
Typical Application Circuit
Features and Benefits
●● High Resolution for Instrumentation Applications that
Require a Wide Dynamic Range
∙ 130dB SNR at 1.9sps
∙ 112dB SNR at 1000sps
∙ 20.4-Bit Noise-Free Resolution at 1.9sps
∙ 17.4-Bit Noise-Free Resolution at 1000sps
●● Longer Battery Life for Portable Applications
∙ 2.4mA Operating Mode Current
∙ 4.4mA PGA Low-Noise Mode Current
∙ 1μA Sleep Current
●● High Accuracy for DC Measurements
∙ 1ppm INL (typ), 4ppm (max)
●● Single or Split Analog Supplies Provide Input Voltage
Range Flexibility
∙ 2.7V to 3.6V (Single Supply) or
±1.8V (Split Supplies)
●● Flexible High-Performance Filter Architecture
Simplifies Design
∙ Programmable SINC Filter
●● Enables System Integration
∙ Low-Noise PGA with Gains of 1, 2, 4, 8, 16, 32,
64, 128
∙ Signal Buffer Optional
∙ 3 General-Purpose I/Os
●● Enables Integrated Part and System Calibration for
Gain and Offset
●● Robust 24-Pin TSSOP Packaging
AINP
10nF
C0G
AINN
2.7V TO 3.6V
REF
10nF 1µF 2.0V TO 3.6V
REFN REFP
MAX11270
AVDD
DVDD
RST
SYNC
CSB
SCLK
DIN
DOUT
RDY
µC
1µF
GPIO3 GPI02 GPI01
CAPP CAPN CAPREG AVSS AVSS DGND
1µF
0603
10nF X7R
C0G
19-7048; Rev 0; 8/14
1 page  
MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
LIST OF TABLES
Table 1. Continuous Mode SNR (dB) vs Data Rate and PGA Gain with Sinc Filter* . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 2. Continuous Mode Input-Referred Noise (µVRMS) vs. Data Rate and PGA Gain with Sinc Filter* . . . . . . . . . 19
Table 3. Single-Cycle Mode SNR (dB) vs. Data Rate and PGA Gain with Sinc Filter* . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4. Single-Cycle Mode Input-Referred Noise (µVRMS) vs. Data Rate and PGA Gain with Sinc Filter* . . . . . . . 21
Table 5. MAX11270 Command Behavior from Pin (RSTB, SYNC) and SPI (RESET, SYNC_SPI) . . . . . . . . . . . . . . . . . . . . 22
Table 6. Command Byte for Conversion Modes (MODE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Command Byte for Register Access Mode (MODE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 8. Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. Programmable Conversion Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. ADC Output Code Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 11. MODBITS Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Maxim Integrated │ 5
5 Page 
MAX11270
24-Bit, 10mW, 130dB SNR, 64ksps Delta-Sigma
ADC with Integrated PGA
Typical Operating Characteristics (continued)
(VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V, VREFP = 2.5V, VREFN = 0V; fDATA = 1000sps, External Clock = 8.192MHz; Continuous
conversion mode (SCYCLE = 0); PGA maximum output is 300mV below AVDD and minimum output is 300mV above AVSS,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
64ksps NOISE HISTOGRAM
450 toc09
400
350
300
250
200
150
100 BYPASS MODE
50
SINC FILTER
SHORTED INPUTS
0
-80-70-60-50-40-30-20-10 0 10 20 30 40 50 60 70 80
NOISE (µV)
INL vs INPUT VOLTAGE
toc10C
1
0.8
TA =+85°C
PGA = 4 LN Mode
0.6 TA =+25°C
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8 TA = -40°C
-1
-0.65
-0.325 0 0.325
DIFFERENTIAL INPUT (V)
0.65
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-2.5
INL vs. INPUT VOLTAGE
toc10A
Bypass Mode
TA = +85°C
TA = +25°C
TA = -40°C
-1.5 -0.5 0.5 1.5
DIFFERENTIAL INPUT (V)
2.5
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.65
INL vs. INPUT VOLTAGE
toc10D
TA = -40°C PGA = 4 LP Mode
TA = +85°C
TA = +25°C
-0.325 0 0.325
DIFFERENTIAL INPUT (V)
0.65
INL vs. INPUT VOLTAGE
1 toc10B
Buffer Mode
0.8
0.6
0.4
0.2 TA = +85°C
0
-0.2 TA = +25°C
-0.4
-0.6
-0.8 TA = -40°C
-1
-2.5
-1.5 -0.5 0.5 1.5
DIFFERENTIAL INPUT (V)
2.5
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50
OFFSET ERROR
vs. TEMPERATURE
toc11
CALIBRATED AT 25°C
BYPASS MODE
0 50 100
TEMPERATURE (°C)
150
OFFSET ERROR
vs. AVDD
7 toc12
CALIBRATED AT VAVDD = 3.15V
6 BYPASS MODE
5
4
3
2
1
0
2.5
3 3.5
VAVDD (V)
4
10
9
8
7
6
5
4
3
2
1
0
1
SELF CALIBRATION OFFSET ERROR
vs. VREFP - VREFN
toc13
BYPASS MODE
23
VREFP - VREFN (V)
4
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX11270.PDF ] | |
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