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PDF MBM29F040C-70 Data sheet ( Hoja de datos )
| Número de pieza | MBM29F040C-70 | |
| Descripción | 4M (512K X 8) BIT FLASH MEMORY | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
4M (512K × 8) BIT
DS05-20842-4E
MBM29F040C-55/-70/-90
s FEATURES
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Single 5.0 V read, program and erase
Minimizes system level power requirements
Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
Compatible with JEDEC-standard byte-wide pinouts
32-pin PLCC (Package suffix: PD)
32-pin TSOP(I) (Package suffix: PF)
32-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
Minimum 100,000 write/erase cycles
High performance
55 ns maximum access time
Sector erase architecture
8 equal size sectors of 64K bytes each
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Embedded Erase™ Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded Program™ Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Low VCC write inhibit ≤ 3.2 V
Sector protection
Hardware method disables any combination of sectors from write or erase operations
Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.
1 page  
s PRODUCT LINE UP
Part No.
Ordering Part No.
VCC = 5.0 V ±5%
VCC = 5.0 V ±10%
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
s BLOCK DIAGRAM
MBM29F040C-55/-70/-90
MBM29F040C
-55 —
—
— -70 -90
55 70 90
55 70 90
30 30 35
VCC
VSS
WE
CE
OE
DQ0 to DQ7
Erase Voltage
Generator
Input/Output
Buffers
State
Control
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
STB Data Latch
A0 to A18
STB Y-Decoder
Low VCC Detector
Timer for
Program/Erase
Address
Latch
X-Decoder
Y-Gating
Cell Matrix
5
5 Page 
MBM29F040C-55/-70/-90
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A16, A17 and A18) while (A6, A1, A0) = (0,
1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will read
00H for unprotected sector. In this mode, the lower order addresses, except for A0, A1 and A6 are DON’T CARES.
Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02H, where the higher order addresses (A16, A17 and A18) are the
sector address will produce a logical “1” at DQ0 for a protected sector. See Table 3 for Autoselect codes.
Command
Sequence
Read/Reset
Table 5 MBM29F040C Command Definitions
Bus
Write
Cycles
Req'd
First Bus Second Bus
Write Cycle Write Cycle
Addr Data Addr Data
Third Bus
Write Cycle
Addr Data
Fourth Bus
Read/Write
Cycle
Addr Data
Fifth Bus
Write Cycle
Addr Data
Sixth Bus
Write Cycle
Addr Data
Read/Reset*
1 XXXH F0H — — — — — — — — — —
Read/Reset*
4 555H AAH 2AAH 55H 555H F0H RA RD — — — —
Autoselect
3 555H AAH 2AAH 55H 555H 90H — — — — — —
Byte Program
4 555H AAH 2AAH 55H 555H A0H PA PD — — — —
Chip Erase
6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Sector Erase
6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H
Sector Erase Suspend Erase can be suspended during sector erase with Addr (“H” or “L”). Data (B0H)
Sector Erase Resume Erase can be resumed after suspend with Addr (“H” or “L”). Data (30H)
Notes: 1. Address bits A11 to A18 = X = “H” or “L” for all address commands except for Program Address (PA) and
Sector Address (SA).
2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the
WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, and A16 will uniquely select any
sector.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of WE.
*: Either of the two reset commands will reset the device.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the device to read
mode. Table 5 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase
Resume (30H) commands are valid only while the Sector Erase operation is in progress. Moreover, both Read/
Reset Commands are functionally equivalent, resetting the device to the read mode.
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MBM29F040C-70.PDF ] | |
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