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PDF LTC6905-80 Data sheet ( Hoja de datos )
| Número de pieza | LTC6905-80 | |
| Descripción | Fixed Frequency SOT-23 Oscillator | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
■ No External Components to Set Frequency
■ Frequency Error ±0.5% Typical
■ Fast Start-Up Time: 100µs Typical
■ ±20ppm/°C Temperature Stability
■ Output Enable Provided
www.DataSh■eetI4nUc.cluomdes Divide by 1, 2 or 4
■ Rise Time: 0.5ns, CL = 5pF
■ Timing Jitter: <0.8% Typical
■ 50% ±2.5% Duty Cycle
■ IS = 8mA Typical (fOSC = 100MHz, CL = 5pF)
■ CMOS Output Drives 600Ω Load
■ Single Supply 2.7V to 5.5V
■ Low Profile (1mm) ThinSOTTM Package
U
APPLICATIO S
■ Data Clocks for High Reliability Applications
■ High Vibration, High Acceleration Environments
■ Replacement for Fixed Crystal and Ceramic
Oscillators
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6614313, 6342817.
TYPICAL APPLICATIO
3V
0.1µF
Basic Connection
fOSC = 133MHz
1 V+
5
OUT
LTC6905-133
2
GND
3
OE
4
DIV
3V
÷1
÷2
OPEN
6905x TA01
÷4
LTC6905-XXX Series
Fixed Frequency
SOT-23 Oscillator
DESCRIPTIO
The LTC®6905-XXX series of parts are precision, fixed
frequency, silicon oscillators designed to minimize board
space while maximizing accuracy and ease of use.
Programmed at the factory to a fixed frequency, the
LTC6905-XXX series of parts need no external trim com-
ponents. An internal three-state divider allows for division
of the master clock by 1, 2 or 4, providing 3 frequencies
(for each device).
The LTC6905-XXX series operate with a single 2.7V to
5.5V power supply and provide a rail-to-rail, 50% duty
cycle, square wave output. The OE pin will disable the
output when brought low and synchronously enable the
output when brought high, avoiding pulse slivers.
The four products of the LTC6905-XXX family are:
LTC6905-133: fOSC = 133MHz, 66.7MHz, 33.3MHz
LTC6905-100: fOSC = 100MHz, 50MHz, 25MHz
LTC6905-96: fOSC = 96MHz, 48MHz, 24MHz
LTC6905-80: fOSC = 80MHz, 40MHz, 20MHz
The LTC6905-XXX series of parts are designed with a factory
trim option to modify the divider ratios from 1, 2, 4 to 8, 16,
32. A second trim option allows for additional master clock
frequencies. For the alternate divider ratios and unlisted
frequencies, contact LTC marketing.
Typical Distribution of Frequency Error, TA = 25°C
40
VS = 3V
30
20
10
0
–1 –0.5 0.0 0.5
1
% FREQUENCY ERROR 6905x TA02
6905xf
1
1 page  
LTC6905-XXX Series
PI FU CTIO S
V+ (Pin 1): Voltage Supply (2.7V ≤ V+ ≤ 5.5V). This supply
must be kept free from noise and ripple. It should be
bypassed directly to the GND (Pin 2) with a 0.1µF capacitor
or higher.
GND (Pin 2): Ground. Should be tied to a ground plane for
best performance.
OE (Pin 3): Output Enable. Pull to V+ or leave floating to
www.DataSheeneat4bUle.cotmhe output driver (Pin 5). Pull low to disable the
output. The output is disabled asynchronously. Pulling OE
pin low will immediately disable the output. Pulling the OE
pin high will bring the output high on the next low to high
transition of the clock. This eliminates pulse slivers.
DIV (Pin 4): Divider-Setting Input. This three-state input
selects among three divider settings. Pin 4 should be tied
to V+ for the ÷1 setting, the highest frequency range. Float-
ing Pin 4 divides the master oscillator by 2. Pin 4 should
be tied to GND for the ÷4 setting, the lowest frequency range.
To detect a floating DIV pin, the LTC6905 attempts to pull
the pin toward midsupply. This is realized with two internal
current sources, one tied to V+ and Pin 4 and the other one
tied to ground and Pin 4. Therefore, driving the DIV pin high
requires sourcing approximately 15µA. Likewise, driving
DIV low requires sinking 15µA. When Pin 4 is floated, it
should be bypassed by a 1nF capacitor to ground or it should
be surrounded by a ground shield to prevent excessive cou-
pling from other PCB traces.
OUT (Pin 5): Oscillator Output. This pin can drive 5kΩ
and/or 5pF loads. For heavier loads, refer to the Applica-
tions Information section.
BLOCK DIAGRA
V+
1
RSET IRES
VR(EVS+
=
–
1V ±5%
VSET)
+
GAIN = 1
–
MASTER OSCILLATOR
+–
2 GND
VBIAS
–
+
IRES
3
OE
PROGRAMMABLE
fOSC
=
fMO
N
OUT
DIVIDER
5
(N = 1, 2 OR 4)
DIVIDER
SELECT
fMO
THREE-STATE
INPUT DETECT
V+
15µA
DIV
4
15µA
GND
6905x BD
Table 1. LTC6905-XXX Frequency Settings
DIV SETTING LTC6905-133 LTC6905-100
V+
133.33MHz
100MHz
OPEN
66.66MHz
50MHz
GND
33.33MHz
25MHz
LTC6905-96
96MHz
48MHz
24MHz
LTC6905-80
80MHz
40MHz
20MHz
6905xf
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LTC6905-80.PDF ] | |
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