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PDF TH7834C Data sheet ( Hoja de datos )
| Número de pieza | TH7834C | |
| Descripción | Very High resolution Linear CCD Image Sensor | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 6.5 µm x 6.5 µm Photodiode Pixel, at 6.5 µm Pitch
• 2 x 2 Outputs
• High Output Data Rate: 4 x 5 MHz
• High Dynamic Range: 10000: 1
• Antiblooming and Exposure Time Control
• Very Low Lag
• 56 lead 0.6" DIL Package
Description
Atmel’s TH7834C is a linear sensor based on charge-coupled device (CCD) technol-
ogy. It can be used in a wide range of applications thanks to operating mode flexibility,
very high definition and high dynamic range (document scanning, digital photography,
Art, Industrial and Scientific Applications).
Pixel 1
mark
VOS1
VDR1
VS1
ΦR1-2
VSS
VST
ΦA1-2
VGS1-2
VS
Φ3A
Φ1A
Φ4A
Φ2A
VSS
VSS
Φ2C
Φ4C
Φ1C
Φ3C
VSS
ΦP3-4
VA3-4
ΦLS3-4
VSS
VDD3-4
VS3
VDR3
VOS3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VOS2
55 VDR2
54 VS2
53 VDD1-2
52 VSS
51 ΦLS1-2
50 VA1-2
49 ΦP1-2
48 VSS
47 Φ3D
46 Φ1D
45 Φ4D
44 Φ2D
43 VSS
42 VSS
41 Φ2B
40 Φ4B
39 Φ1B
38 Φ3B
37 VSS
36 VGS3-4
35 ΦA3-4
34 VST
33 VSS
32 ΦR3-4
31 VS4
30 VDR4
29 VOS4
Very High-
resolution
Linear CCD
Image Sensor
(12000 Pixels)
TH7834C
TOP VIEW
Rev. 1997A–IMAGE–05/02
1
1 page  
TH7834C
Readout Shift Register
Clocking
All gates of the 4 CCD shift registers are separated, enabling two or four output readout
modes.
To select 2 or 4 outputs operating mode, register main transport gates must be con-
nected as described here after:
• 4 outputs mode:
VOS1: ΦL1 = Φ2A + Φ3A; ΦL2 = Φ1A + Φ4A
VOS2: ΦL1 = Φ2B + Φ3B; ΦL2 = Φ1B + Φ4B
VOS3: ΦL1 = Φ2C + Φ3C; ΦL2 = Φ1C + Φ4C
VOS4: ΦL1 = Φ2D + Φ3D; ΦL2 = Φ1D + Φ4D
• 2 output mode: VOS1 and VOS2:
VOS1: ΦL1 = Φ2A + Φ3A + Φ1C + Φ2C
ΦL2 = Φ1A + Φ4A + Φ3C + Φ4C
VOS2: ΦL1 = Φ2B + Φ3B + Φ1D + Φ2D
ΦL2 = Φ1B + Φ4B + Φ3D + Φ4D
• 2 output mode: VOS3 and VOS4:
VOS3: ΦL1 = Φ1A + Φ2A + Φ2C + Φ3C
ΦL2 = Φ3A + Φ4A + Φ1C + Φ4C
VOS4: ΦL1 = Φ1B + Φ2B + Φ2D + Φ3D
ΦL2 = Φ3B + Φ4B + Φ1D + Φ4D
Note: In 2 output mode, the unused outputs can be connected as following:
• ΦLS = ΦR = VGS = 0V
• 10V < VDR < 15V
• VDD = 15V
• VS not connected in order to cancel unused output amplifiers power consumption.
Absolute Maximum Ratings*
Storage Temperature ................................... -55°C to + 150°C
Operating Temperature ................................. 0°C to + 70°C
Thermal Cycling.........................................................15°C/mm
Maximum Voltage:
• Pins: 4, 6, 7, 8, 10, 11, 12, 13, 16, 17, 18,
19, 21, 23, 32, 34, 35, 36, 38, 39, 40, 41, 44,
45, 46, 47, 49, 51...............................................-0.3V to + 15V
• Pins: 2, 3, 22, 25, 26, 27, 30,
31, 50, 53, 54, 55............................................-0.3V to + 15.5V
• Pins: 5, 9, 14, 15, 20, 24, 33, 37, 42, 43, 48, 52 .. Ground 0V
*NOTICE:
Stresses above those listed under absolute max-
imum ratings may cause permanent device fail-
ure. Functionality at or above these limits is not
implied. Exposure to absolute maximum ratings
for extended periods may affect reliability.
Operating Range
Operating range defines the temperature limits between which the functionality is guar-
anteed: 0°C to 70°C.
1997A–IMAGE–05/02
5
5 Page 
Exposure Time
Reduction (See
Figure 8)
1997A–IMAGE–05/02
TH7834C
Figure 6. Typical Spectral Responsitivity
8.0
η=0.8
η=0.7
7.2
η=0.6
6.4
5.6
4.8
4.0
3.2
2.4
1.6
0.8
0
400 500 600 700 800 900 1000 1100
Lambda (nm)
Figure 7. VSAT versus ΦA Low Level Typical Curve
Antiblooming
OFF
Antiblooming
ON
3600
3400
3200
3000
2800
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
0
VST = 4 V
ΦR Low level = 1.5V
VA = 13V
1 2 3 4 5 6 7 8 8.5
ΦA bias (V)
TH7834 allows a reduction in the exposure time without changing the readout time. It
thus provides a function which is equivalent to an optical iris.
The exposure time reduction consists in increasing the ΦA gate bias in order to remove
continuously, during period 2, the photoelectrons from the pixel and to inject them into
the antiblooming diode VA. When ΦA returns to the normal bias, electrons are integrated
in the pixel.
Only excess electrons are evacuated into VA (blooming control). Thus, the actual inte-
gration time is ti instead of Ti, without any change in the readout sequence. Register
transfer and reset clocks (ΦL, ΦLS and ΦR) must be pulsed during the Ti integration time.
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet TH7834C.PDF ] | |
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