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PDF HD68A21 Data sheet ( Hoja de datos )
| Número de pieza | HD68A21 | |
| Descripción | Peripheral Interface Adapter | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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HD6821, HD68A21, HD68B21
P I A (Peripheral Interface Adapter)
The HD6821 Peripheral Interface Adapter provides the
universal means of interfacing peripheral equipment to the
HD6800 Microprocessing Unit (MPU)- This device is capable
of interfacing the MPU to peripherals through two 8-bit
bi-directional peripheral data buses and four control lines. No
external logic is required for interfacing to most peripheral
devices.
The functional configuration of the PIA is programmed by
the MPU during system initialization. Each of the peripheral
data lines can be programmed to act as an input or output, and
each of the four control/interrupt lines may be programmed for
one of several control modes. This allows a high degree of
flexibility in the over-all operation of the interface.
HD6821P, HD68A21P, HD68B21P
(DP-40)
FEATURES
Two Bi-directional 8-Bit Peripheral Data Bus for interface to
Peripheral devices
Two Programmable Control Registers
Two Programmable Data Direction Registers
Four Individually-Controlled Interrupt Input Lines: Two
Usable as Peripheral Control Outputs
Handshake Control Logic for Input and Output Peri-
pheral Operation
High-Impedance 3-State and Direct Transistor Drive
Peripheral Lines
Program Controlled Interrupt and Interrupt Disable
Capability
CMOS Drive Capability on Side A Peripheral Lines
Two T T L Drive Capability on All A and B Side Buffers
N Channel Silicon Gate MOS
Compatible with MC6821, MC68A21 and MC68B21
• BLOCK
IRQA 38 *
DIAGRAM
rro
Control
Register A
(CRAI
Data But
Buffers
(DBB)
Output
Register A
(OR A)
Oata Direction
Register A
(DORA)
3Z
PIN ARRANGEMENT
VssEI
PA0(2
PA, [7
PA, ( 7
PA,[T
PA4£?
PA, | T
PAT[8
PA, [9
o
PBOQO
PB, (H
PB, [12
PB, {13
PB4 [U
PB,M
PBT[?6
ce,|T8
CB, Q|
Vccl
HD6821
*3 CA,
CA,
IRQA
0 ,RQB
1 RS0
3RS,
3 RES
3 D°
3 0,
0
3 0,
3 D.
H D'
0
3 0,
HE
igcs,
^cs,
3 cs0
3 R/VV
(Top View)
V c c » P i n 20
Vss-Pin 1
Bus Input
Reenter
IBIfi)
Output
Register B
IORBI
R/W
E
RES
21
25
34
Q Control
Register B
ICRS)
21
Date Direction
Register B
IDDRB)
'3 PB,
14 P B .
15 PB,
16 PB.
18 CB,
t9 CB,
0 HITACHI
319
1 page  
Enable
\2.0V
•ff-
CB,
•TCB2'
*RS2
CB, 2.4V
ma-
Assumes part was deselected during
any previous E pulse.
Figure 7 CB2 Delay Time
(Write Mode; CRB5=1, CRB3=CRB4=0)
HD6821 ,HD68A21 ,HD68B21
CA,, CA2
CB,,CB2
IRQA,
IRQB
X2.0V
0.8V
•PWI
LRS3
* Assumes Interrupt Enable Bits are set.
V 4V
Figure 8 Interrupt Pulse Width and IRQ Response
Enable
IRQ
2.0V
t|R
2.4V
/
Figure 9 IRQ Release Time
RES
^ i-0.8V
tRL
^
The RES line must be a V j H for a m i n i m u m of
1.0 ms before addressing the PI A .
Figure 10 RES Low Time
Figure 11 Enable Signal Characteristics
Enable
Enable
tK2.0V
j/o.8V
tAS
RS ov
RC/SWh:
~
Y
~
2
.8V
Data Bus
2.0V-V
tAh
<osw
2.0V £
0.8V \
K" 'DHW
2.0V
0.8V
Figure 12 Bus Read Timing Characteristics
(Read Information from PIA)
Figure 13 Bus Write Timing Characteristics
(Write Information into PIA)
LOAD A
(PAO~PA7 , PB0 ~ P B , , CAa, CB,)
LOAD B
(D0-D7)
LOAD C
(1TO Only)
5.0V
5.0V (VCc)
R,
Test Point
fTii
1 V.
Test Point O-
R l « 2.4W2
Test Point O-
rrr
C-40pF
R»12kfl
C*130pF
R=11kft
rrr
All diodes are1S2074iBor equivalent.
Adjust R L so that I 0 L = 1.6mA, then test V O L A H d i o d e s a r e 1 S 2 0 7 4 ^ o r equivalent.
Adjust R L SO that IQU " 3 . 2 m A , then test V Q L
Figure 14 Bus Timing Test Loads
0 HITACHI
LOAD D
5.0V
3k SI
4=100pF
(CMOS Load) Test Point
O——
<PA0~PA?/CAj)
^
30pF
rrr
323
5 Page 
• Read/Write Operating Using Control Lines
Read/write request from peripherals shall be put into the
control lines as an interrupt signal, and then MPU reads or
writes after detecting interrupt request.
<R««d>
The following case is that Port A is used and that the rising
edge of CAX indicates the request for read from peripherals.
HD6821 ,HD68A21 ,HD68B21
CLR CRA . S e t the DDRA access bit to " 0 " .
CLR DDRA • Set all bits of the data direction register to "0".
LDAA #$06 • Program the rising edge of CAj to be active. IRQA is masked
STAA CRA
^ DDRA access bit is set to 1.
LOOP LDAA CRA
BPL LOOP
Check whether the read request comes from peripherals
or not.
LDAA PIRA
Load the data from the peripheral interface register into the
accumulator. CRA flag is reset after this read operation.
To read the peripheral data, the data is directly transfered to
the data buses D 0 ~ D 7 through PA0~PA7 or PB0~PB, and
they are not latched in the PIA. If necessary, the data should be
held in the external latch until MPU completes reading it.
When initializing the control register, interrupt flag bit
(CRA7, CRA6, CRB7, CRB6) cannot be written from MPU. If
necessary the interrupt flag must be reset by dummy read of
Peripheral Register A and B.
<Wrtta>
Write operation using the interrupt signal is as follows. In
this case. B port is used and interrupt request is input to CBj.
And the IRQ flag is set at the rising edge of CBj.
0 HITACHI
329
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HD68A21.PDF ] | |
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