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PDF ADSP-BF527 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-BF527 | |
| Descripción | Blackfin Embedded Processor | |
| Fabricantes | Analog Devices | |
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Blackfin
Embedded Processor
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations. See Specifications on Page 28
Programmable on-chip voltage regulator (ADSP-BF523/
ADSP-BF525/ADSP-BF527 processors only)
Qualified for Automotive Applications. See Automotive
Products on Page 87
289-ball and 208-ball CSP_BGA packages
MEMORY
132K bytes of on-chip memory (See Table 1 on Page 3 for L1
and L3 memory size details)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI, and TWI
memory or from host devices including SPI, TWI, and UART
Code security with Lockbox Secure Technology
one-time-programmable (OTP) memory
Memory management unit providing memory protection
PERIPHERALS
USB 2.0 high speed on-the-go (OTG) with integrated PHY
IEEE 802.3-compliant 10/100 Ethernet MAC
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Host DMA port (HOSTDP)
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting eight stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 54 interrupt inputs
Serial peripheral interface (SPI) compatible port
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timers/counters with PWM support
32-bit up/down counter with rotary support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), with programmable
hysteresis
NAND flash controller (NFC)
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
VOLTAGE REGULATOR*
WATCHDOG TIMER
JTAG TEST AND EMULATION
PERIPHERAL
ACCESS BUS
B
INTERRUPT
CONTROLLER
L1 INSTRUCTION
MEMORY
EAB 16
USB
L1 DATA
MEMORY
DMA
CONTROLLER
DCB
DEB
DMA
ACCESS
BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
BOOT
ROM
*REGULATOR ONLY AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS
OTP MEMORY
RTC
COUNTER
SPORT0
SPORT1
UART1
UART0
NFC
PPI
SPI
TIMER7-1
TIMER0
EMAC
HOST DMA
TWI
GPIO
PORT F
GPIO
PORT G
GPIO
PORT H
PORT J
Figure 1. Processor Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency on-chip memory as cache
or SRAM, and larger, lower-cost and performance off-chip
memory systems. See Figure 3.
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip
memory system, accessed through the external bus interface
unit (EBIU), provides expansion with SDRAM, flash memory,
and SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high-bandwidth data-
movement capability. It can perform block transfers of code
or data between the internal memory and the external
memory spaces.
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 C000
0xFFA0 8000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 8000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x08 00 0000
0x0000 0000
CORE MMR REGISTERS (2M BYTES)
SYSTEM MMR REGISTERS (2M BYTES)
RESERVED
SCRATCHPAD SRAM (4K BYTES)
RESERVED
INSTRUCTION SRAM / CACHE (16K BYTES)
RESERVED
INSTRUCTION BANK B SRAM (16K BYTES)
INSTRUCTION BANK A SRAM (32K BYTES)
RESERVED
DATA BANK B SRAM / CACHE (16K BYTES)
DATA BANK B SRAM (16K BYTES)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTES)
DATA BANK A SRAM (16K BYTES)
RESERVED
BOOT ROM (32K BYTES)
RESERVED
ASYNC MEMORY BANK 3 (1M BYTES)
ASYNC MEMORY BANK 2 (1M BYTES)
ASYNC MEMORY BANK 1 (1M BYTES)
ASYNC MEMORY BANK 0 (1M BYTES)
RESERVED
SDRAM MEMORY (16M BYTES 128M BYTES)
Figure 3. Internal/External Memory Map
Internal (On-Chip) Memory
The processor has three blocks of on-chip memory providing
high-bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
64K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM), as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
Rev. D | Page 5 of 88 | July 2013
5 Page 
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
• Bidirectional operation — Each SPORT has two sets of
independent transmit and receive pins, enabling eight
channels of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports — Each port
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking — Each transmit and receive port can either use
an external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length – Each SPORT supports serial data words
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
• Framing — Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
• Companding in hardware — Each SPORT can perform
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without
additional latencies.
• DMA operations with single-cycle overhead — Each
SPORT can automatically receive and transmit multiple
buffers of memory data. The processor can link or chain
sequences of DMA transfers between a SPORT and
memory.
• Interrupts — Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer, or buffers,
through DMA.
• Multichannel capability — Each SPORT supports 128
channels out of a 1024-channel window and is compatible
with the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORT
The processors have an SPI-compatible port that enables the
processor to communicate with multiple SPI-compatible
devices.
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSI, and Master Input-
Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI
chip select input pin (SPISS) lets other SPI devices select the
processor, and seven SPI chip select output pins (SPISEL7–1) let
the processor select other SPI devices. The SPI select pins are
reconfigured general-purpose I/O pins. Using these pins, the
SPI port provides a full-duplex, synchronous serial interface,
which supports both master/slave modes and multimaster
environments.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA channel,
configurable to support transmit or receive data streams. The
SPI’s DMA channel can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
SPI Clock Rate = ------------f--S--C---L---K-------------
2 SPI_BAUD
Where the 16-bit SPI_BAUD register contains a value of 2
to 65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
UART PORTS
The processors provide two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. A UART port includes support for five to eight data bits,
one or two stop bits, and none, even, or odd parity. Each UART
port supports two modes of operation:
• PIO (programmed I/O) — The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access) — The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
Each UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from seven to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
UART Clock Rate = ------------------f--S--C---L---K-------------------
16 UART_Divisor
Where the 16-bit UART_Divisor comes from the UART_DLH
(most significant 8 bits) and UART_DLL (least significant
8 bits) registers.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UARTs are further extended with sup-
port for the infrared data association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
Rev. D | Page 11 of 88 | July 2013
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADSP-BF527.PDF ] | |
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