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PDF ADUC7039 Data sheet ( Hoja de datos )
| Número de pieza | ADUC7039 | |
| Descripción | Battery Sensor | |
| Fabricantes | Analog Devices | |
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Integrated, Precision
Battery Sensor for Automotive Systems
ADuC7039
FEATURES
High precision ADC
Dual channel, simultaneous sampling, 16-bit, Σ-Δ ADCs
Programmable ADC throughput from 10 Hz to 1 kHz
On-chip 5 ppm/ºC voltage reference
Current channel
Fully differential, buffered input
Programmable gain
ADC input range: −200 mV to +300 mV
Digital comparator with current accumulator feature
Voltage channel
Buffered, on-chip attenuator for 12 V battery input
Temperature channel
External and on-chip temperature sensor options
Microcontroller
ARM7TDMI-S core, 16-/32-bit RISC architecture
20.48 MHz PLL
On-chip precision oscillator
JTAG port supports code download and debug
Memory
64 kB Flash/EE memory options, 4-kB SRAM
10,000-cycle Flash/EE endurance, 20-year Flash/EE
retention
In-circuit download via JTAG and LIN
On-chip peripherals
LIN 2.1-compatible slave
SPI
GPIO port
1 × general-purpose timer
Wake-up and watchdog timers
On-chip power-on-reset
Power
Operates directly from 12 V battery supply
Current consumption 7.5 mA (10 MHz)
Low power monitor mode
Package and temperature range
32-pin, 6 mm × 6 mm LFCSP
Fully specified for −40°C to +115°C operation
APPLICATIONS
Battery sensing/management for automotive systems
IIN+
IIN–
VBAT
VTEMP
GND_SW
FUNCTIONAL BLOCK DIAGRAM
RTCK TCK TDI TDO NTRST TMS
PRECISION ANALOG ACQUISITION
BUF
PGA
16-BIT
Σ-Δ ADC
ADuC7039
LDO
POR
MEMORY
64KB FLASH
4KB RAM
RESET
RESULT
DIGITAL
ACCUMULATOR COMPARATOR
MUX BUF
16-BIT
Σ-Δ ADC
TEMPERATURE PRECISION
SENSOR
REFERENCE
20MHz
ARM7TDMI
MCU
PRECISION
OSC
LOW POWER
OSC
ON-CHIP PLL
1 × TIMER
WDT
W/U TIMER
GPIO PORT
SPI PORT
LIN
LIN
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
ADuC7039
Parameter
LOGIC INPUTS1
Input Low Voltage (VINL)
Input High Voltage (VINH)
ON-CHIP OSCILLATORS
Low Power Oscillator
Accuracy
Precision Oscillator
Accuracy
MCU CLOCK RATE1
MCU START-UP TIME1
At Power-On
After Reset Event
From MCU Power-Down
Internal PLL Lock Time
LIN I/O GENERAL
Baud Rate
VDD
Input Capacitance1
LIN Comparator Response Time1
LIN DC PARAMETERS
ILIN DOM MAX
I1
LIN_PAS_REC
I1
LIN_PAS_DOM
I 1, 20
LIN_NO_GND
I1
BUS_NO_BAT
V1
LIN_DOM
V1
LIN_REC
V1
LIN_CNT
VHYS1
V1
LIN_DOM_DRV_LOSUP
RL 500 Ω
RL 1000 Ω
V1
LIN_DOM_DRV_HISUP
RL 500 Ω
RL 1000 Ω
VLIN_RECESSIVE1
VBAT Shift20
GND Shift20
RSLAVE
V 20
SERIAL DIODE
LIN AC PARAMETERS1
D1
D2
Test Conditions/Comments
All logic inputs
After user calibration at nominal supply and room
temperature; includes drift data from 1000 hr life-test
After run time calibration
Includes kernel power-on execution time
Includes kernel power-on execution time
Oscillator running
Supply voltage range for which the LIN interface is functional
Using 22 Ω resistor
Current limit for driver when LIN bus is in dominant state;
VBAT = VBAT (maximum)
Driver off; 7.0 V < VBUS < 18 V; VDD = VLIN − 0.7 V
Input leakage, VLIN = 0 V
Control unit disconnected from ground, GND = VDD;
0 V < VLIN < 18 V; VBAT = 12 V
VBAT disconnected, VDD = GND, 0 V < VBUS < 18 V
LIN receiver dominant state, VDD > 7.0 V
LIN receiver recessive state, VDD > 7.0 V
LIN receiver center voltage, VDD > 7.0 V
LIN receiver hysteresis voltage
LIN dominant output voltage; VDD = 7.0 V
LIN dominant output voltage; VDD = 18 V
LIN recessive output voltage
Slave termination resistance
Voltage drop at the serial diode, DSer_Int
Bus load conditions (CBUS||RBUS):
1 nF||1 kΩ; 6.8 nF||660 Ω; 10 nF||500 Ω
Duty Cycle 1
THREC(MAX) = 0.744 × VBAT
THDOM(MAX) = 0.581 × VBAT
VSUP = 7.0 V … 18 V; tBIT = 50 μs
D1 = tBUS_REC(MIN)/(2 × tBIT)
Duty Cycle 2
THREC(MIN) = 0.284 × VBAT
THDOM(MIN) = 0.422 × VBAT
VSUP = 7.0 V…18 V; tBIT = 50 μs
D2 = tBUS_REC(MAX)/(2 × tBIT)
Min Typ
2.0
−3
−1
1000
7
40
128
128
10.24
25
5
2
1
5.5
38
−1
−1
0.6 VDD
0.475 VDD 0.5 VDD
0.6
0.8
0.8 VDD
0
0
20
0.4
30
0.7
0.396
Max Unit
0.4 V
V
kHz
+3 %
kHz
+1 %
MHz
ms
ms
ms
ms
20,000
18
90
Bits/sec
V
pF
μs
200 mA
20 μA
mA
+1 mA
100
0.4 VDD
0.525 VDD
0.175 VDD
μA
V
V
V
V
1.2 V
V
2
0.115 VDD
0.115 VDD
47
1
V
V
V
V
V
kΩ
V
0.581
Rev. 0 | Page 5 of 88
5 Page 
TERMINOLOGY
Conversion Rate
The conversion rate specifies the rate at which an output result
is available from the ADC, after the ADC has settled.
The sigma-delta (Σ-Δ) conversion techniques used on this part
mean that while the ADC front-end signal is oversampled at a
relatively high sample rate, a subsequent digital filter is used to
decimate the output giving a valid 16-bit data conversion result
at output rates from 1 Hz to 1 kHz.
Note that when software switches from one input to another
(on the same ADC), the digital filter must first be cleared and
then allowed to average a new result. Depending on the con-
figuration of the ADC and the type of filter, this can require
multiple conversion cycles.
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight
line passing through the endpoints of the transfer function.
The endpoints of the transfer function are zero scale, a point
½ LSB below the first code transition, and full scale, a point ½
LSB above the last code transition (111 . . . 110 to 111 . . . 111).
The error is expressed as a percentage of full scale.
No Missing Codes
No missing codes is a measure of the differential nonlinearity
of the ADC. The error is expressed in bits and specifies the
number of codes (ADC results) as 2N bits, where N = no
missing codes, guaranteed to occur through the full ADC
input range.
Offset Error
Offset error is the deviation of the first code transition ADC
input voltage from the ideal first code transition.
Offset Error Drift
Offset error drift is the variation in absolute offset error with
respect to temperature. This error is expressed as LSB/°C
or nV/°C.
Gain Error
Gain error is a measure of the span error of the ADC. It is a
measure of the difference between the measured and the ideal
span between any two points in the transfer function.
ADuC7039
Output Noise
The output noise is specified as the standard deviation (or 1 × Σ)
of ADC output codes distribution collected when the ADC
input voltage is at a dc voltage. It is expressed as μV or nV rms.
The output, or rms noise, can be used to calculate the effective
resolution of the ADC as defined by the following equation:
Effective Resolution = log2(Full-Scale Range/rms Noise) bits
The peak-to-peak noise is defined as the deviation of codes that
fall within 6.6 × Σ of the distribution of ADC output codes col-
lected when the ADC input voltage is at dc. The peak-to-peak
noise is, therefore, calculated as 6.6 × the rms noise.
The peak-to-peak noise can be used to calculate the ADC
(noise free, code) resolution for which there is no code flicker
within a 6.6 × Σ limit as defined by the following equation:
Noise Free Code Resolution = log2(Full-Scale Range/Peak-
to-Peak Noise) bits
Table 4. Data Sheet Acronyms
Acronym
Definition
ADC Analog-to-digital converter
ARM Advanced RISC machine
JTAG
Joint test action group
LIN Local interconnect network
LSB Least significant byte/bit
MCU
Microcontroller
MMR
Memory mapped register
MSB Most significant byte/bit
OTP One time programmable
PID Protected identifier
POR Power-on reset
rms Root mean square
Rev. 0 | Page 11 of 88
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADUC7039.PDF ] | |
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