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Lattice Semiconductor - High Performance E2CMOS FPLA Generic Array Logic

Numéro de référence GAL6001B-30LP
Description High Performance E2CMOS FPLA Generic Array Logic
Fabricant Lattice Semiconductor 
Logo Lattice Semiconductor 





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GAL6001B-30LP fiche technique
GAL6001
High Performance E2CMOS FPLA
Generic Array Logic™
Features
Functional Block Diagram
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
30ns Maximum Propagation Delay
27MHz Maximum Frequency
12ns Maximum Clock to Output Delay
TTL Compatible 16mA Outputs
UltraMOS® Advanced CMOS Technology
LOW POWER CMOS
90mA Typical Icc
INPUT
CLOCK
{INPUTS
2-11
ICLK
2
11
ILMC
AND
OUTPUT
ENABLE
14
23
IOLMC
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
UNPRECEDENTED FUNCTIONAL DENSITY
78 x 64 x 36 FPLA Architecture
10 Output Logic Macrocells
8 Buried Logic Macrocells
20 Input and I/O Logic Macrocells
HIGH-LEVEL DESIGN FLEXIBILITY
Asynchronous or Synchronous Clocking
Separate State Register and Input Clock Pins
Functional Superset of Existing 24-pin PAL®
and FPLA Devices
0
7
BLMC
D
E
OR
14
D 23
OLMC
E
OCLK
Macrocell Names
ILMC INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
BLMC BURIED LOGIC MACROCELL
OLMC OUTPUT LOGIC MACROCELL
{ OUTPUTS
14 - 23
OUTPUT
CLOCK
APPLICATIONS INCLUDE:
Sequencers
State Machine Control
Multiple PLD Device Integration
Description
Using a high performance E2CMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24-
pin, 300-mil package.
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Advanced features that simplify programming and reduce test time,
coupled with E2CMOS reprogrammable cells, enable 100% AC, DC,
programmability, and functionality testing of each GAL6001 during
manufacture. As a result, Lattice Semiconductor delivers 100% field
programmability and functionality of all GAL products. In addition,
100 erase/write cycles and data retention in excess of 20 years are
specified.
Pin Names
I0 - I10
ICLK
OCLK
INPUT
INPUT CLOCK
OUTPUT CLOCK
I/O/Q
VCC
GND
BIDIRECTIONAL
POWER (+5)
GROUND
Pin Configuration
PLCC
4
I5
I
I7
NC
I9
I
I 11
12
2 28 26
25 I/O/Q
GAL6001
Top View
I/O/Q
23 I/O/Q
NC
21 I/O/Q
I/O/Q
19 I/O/Q
14 16 18
DIP
I/ICLK 1
I
24 Vcc
I/O/Q
I I/O/Q
I GAL
I
I 6 6001
I/O/Q
I/O/Q
I/O/Q
I 18 I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
GND 12
13 OCLK
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
July 1997
6001_02
1

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