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PDF M306V7FJAFP Data sheet ( Hoja de datos )
| Número de pieza | M306V7FJAFP | |
| Descripción | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER | |
| Fabricantes | Renesas | |
| Logotipo |  |
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M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
REJ03B0094-0100Z
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Rev.1.00
with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER May 18, 2004
1. DESCRIPTION
The M306V7MG/MH/MJ/MJA-XXXFP and M306V7FG/FH/FJ/FJAFP are single-chip microcomputers us-
ing the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged
in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instruc-
tions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of
executing instructions at high speed. They also feature a built-in OSD display function and data slicer,
making them ideal for closed caption and ID1 for 525p.
1.1 Features
• Memory size ........................................ Refer to Figure 1.5.1 ROM development
<RAM> 10K bytes to 16K bytes
<OSD ROM> 60K bytes
<OSD RAM> 2.2K bytes
• Shortest instruction execution time ...... 62.5 ns (f(XIN)=16 MHz)
• Power source voltage .......................... VCCE (5V system I/O power supply) 4.75 V to 5.25V
VCCI (internal logic power supply) 3.15 V to 3.45V
• Power consumption ............................. 415mW
• Interrupts .............................................. 22 internal and 3 external interrupt sources, 4 software
interrupt sources; 7 levels
• Multifunction 16-bit timer ...................... 2 output timers + 3 input timers + 3 timers
• Serial I/O .............................................. 4 units
UART/clock synchronous: 2
Multi-master I2C-BUS interface 0 (2 systems): 1
Multi-master I2C-BUS interface 1 (1 system): 1
• DMAC .................................................. 2 channels (trigger: 23 sources)
• A-D converter ....................................... 8 bits ✕ 6 channels
• D-A converter ....................................... 8 bits ✕ 2 channels
• Data slicer ............................................ 2 circuits (closed caption and video ID for 525p are available)
• HSYNC counter ..................................... 1 circuit (2 systems)
• OSD function ....................................... 1 circuit
• Watchdog timer .................................... 1 circuit
• Programmable I/O ............................... 76 lines
• Memory expansion .............................. Available
• Chip select output ................................ 4 lines
• Clock generating circuit ....................... 3 built-in clock generation circuits
1.2 Applications
TV with a closed caption and ID1
Rev.1.00 May 18, 2004 page 1 of 296
1 page  
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
1.5 Performance Outline
Table 1.5.1 is a performance outline.
Table 1.5.1 Performance outline
Item Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
62.5 ns(f(XIN)=16 MHz)
Memory
ROM
Refer to Figure 1.5.1 ROM development
size RAM
10K bytes to 16K bytes
OSD ROM
60K bytes
OSD RAM
2.2K bytes
I/O port
P0 to P10
8 bits ✕ 7, 6 bits ✕ 1, 5 bits ✕ 2, 4 bits ✕ 1
Multifunction TA0, TA1, TA2, TA3, TA4
16 bits ✕ 5
timer
TB0, TB1, TB2
16 bits ✕ 3
Serial I/O
UART0
1 unit: UART or clock synchronous
UART2
1 unit: UART or clock synchronous
Multi-master I2C-BUS interface 0 1 unit (2 channels)
Multi-master I2C-BUS interface 1 1 unit (1 channel)
A-D converter
8 bits ✕ 6 channels
D-A converter
8 bits ✕ 2 channels
DMAC
2 channels (trigger: 23 sources)
OSD function
Data slicer
HSYNC counter
Watchdog timer
Data slicer0
Data slicer1
Triple layer, 890 kinds of fonts, 42 characters ✕ 16 lines
16-bit ✕ 2, or data buffer of 16-bit and 20-bit
16-bit ✕ 2, or data buffer of 16-bit and 20-bit
8 bits ✕ 2 channels
15 bits ✕ 1 (with prescaler)
Interrupt
22 internal and 3 external sources, 4 software sources, 7 levels
Clock generating circuit
3 built-in clock generation circuits
Power source voltage VCCE(5V system I/O power supply) 4.75 V to 5.25V
VCCI(internal logic power supply) 3.15 V to 3.45V
Power consumption
415mW
I/O I/O withstand voltage 3.3 V (only P67, P70, P71, P72, P93 and P94 : 5V )
characteristics Output current
5 mA
Memory expansion
Operating ambient temperature
Available
–20 o C to 70 o C
Device configuration
CMOS high performance silicon gate
Package
100-pin plastic molded QFP
Rev.1.00 May 18, 2004 page 5 of 296
5 Page 
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Processor mode register 0 (PM0)
Processor mode register 1 (PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Chip select control register (CSR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
DMA0 source pointer (SAR0)
DMA0 destination pointer (DAR0)
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
DMA1 source pointer (SAR1)
DMA1 destination pointer (DAR1)
DMA1 transfer counter (TCR1)
DMA1 control register (DM1CON)
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
OSD1 interrupt control register (OSD1IC)
Data slicer 1 interrupt control register (DS1IC)
Interrupt control reserved register 1 (RE1IC)
Interrupt control reserved register 2 (RE2IC)
OSD2 interrupt control register (OSD2IC)
Multi-master I2C-BUS interface 1 interrupt control register (IIC1IC)
Bus collision detection interrupt control register (BCNIC)
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
Multi-master I2C-BUS interface 0 interrupt control register (IIC0IC)
A-D conversion interrupt control register (ADIC)
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
Data slicer 0 interrupt control register (DS0IC)
VSYNC interrupt control register (VSYNCIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
Interrupt control reserved register 3 (RE3IC)
01FF16
Figure 2.1.2 Location of peripheral unit control registers (1)
Rev.1.00 May 18, 2004 page 11 of 296
11 Page | ||
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