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M306V7MG-XXXFP fiches techniques PDF

Renesas - SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Numéro de référence M306V7MG-XXXFP
Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fabricant Renesas 
Logo Renesas 





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M306V7MG-XXXFP fiche technique
M306V7MG/MH/MJ/MJA-XXXFP, M306V7FG/FH/FJ/FJAFP
REJ03B0094-0100Z
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Rev.1.00
with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER May 18, 2004
1. DESCRIPTION
The M306V7MG/MH/MJ/MJA-XXXFP and M306V7FG/FH/FJ/FJAFP are single-chip microcomputers us-
ing the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged
in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instruc-
tions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of
executing instructions at high speed. They also feature a built-in OSD display function and data slicer,
making them ideal for closed caption and ID1 for 525p.
1.1 Features
• Memory size ........................................ Refer to Figure 1.5.1 ROM development
<RAM> 10K bytes to 16K bytes
<OSD ROM> 60K bytes
<OSD RAM> 2.2K bytes
• Shortest instruction execution time ...... 62.5 ns (f(XIN)=16 MHz)
• Power source voltage .......................... VCCE (5V system I/O power supply) 4.75 V to 5.25V
VCCI (internal logic power supply) 3.15 V to 3.45V
• Power consumption ............................. 415mW
• Interrupts .............................................. 22 internal and 3 external interrupt sources, 4 software
interrupt sources; 7 levels
• Multifunction 16-bit timer ...................... 2 output timers + 3 input timers + 3 timers
• Serial I/O .............................................. 4 units
UART/clock synchronous: 2
Multi-master I2C-BUS interface 0 (2 systems): 1
Multi-master I2C-BUS interface 1 (1 system): 1
• DMAC .................................................. 2 channels (trigger: 23 sources)
• A-D converter ....................................... 8 bits 6 channels
• D-A converter ....................................... 8 bits 2 channels
• Data slicer ............................................ 2 circuits (closed caption and video ID for 525p are available)
• HSYNC counter ..................................... 1 circuit (2 systems)
• OSD function ....................................... 1 circuit
• Watchdog timer .................................... 1 circuit
• Programmable I/O ............................... 76 lines
• Memory expansion .............................. Available
• Chip select output ................................ 4 lines
• Clock generating circuit ....................... 3 built-in clock generation circuits
1.2 Applications
TV with a closed caption and ID1
Rev.1.00 May 18, 2004 page 1 of 296

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