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GAL20RA10B-10LJ fiches techniques PDF

Lattice Semiconductor - High-Speed Asynchronous E2CMOS PLD Generic Array Logic

Numéro de référence GAL20RA10B-10LJ
Description High-Speed Asynchronous E2CMOS PLD Generic Array Logic
Fabricant Lattice Semiconductor 
Logo Lattice Semiconductor 





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GAL20RA10B-10LJ fiche technique
GAL20RA10
High-Speed Asynchronous E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
HIGH PERFORMANCE E2CMOS ® TECHNOLOGY
7.5 ns Maximum Propagation Delay
Fmax = 83.3 MHz
9 ns Maximum from Clock Input to Data Output
TTL Compatible 8 mA Outputs
UltraMOS® Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
75mA Typical Icc
ACTIVE PULL-UPS ON ALL PINS
E2 CELL TECHNOLOGY
Reconfigurable Logic
Reprogrammable Cells
100% Tested/100% Yields
High Speed Electrical Erasure (<100 ms)
20 Year Data Retention
TEN OUTPUT LOGIC MACROCELLS
Independent Programmable Clocks
Independent Asynchronous Reset and Preset
Registered or Combinatorial with Polarity
Full Function and Parametric Compatibility with
PAL20RA10
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
100% Functional Testability
APPLICATIONS INCLUDE:
State Machine Control
Standard Logic Consolidation
Multiple Clock Logic Designs
ELECTRONIC SIGNATURE FOR IDENTIFICATION
PL
I
I
I
I
I
I
I
I
I
I
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
OLMC
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Description
OE
The GAL20RA10 combines a high performance CMOS process
with electrically erasable (E2) floating gate technology to provide
the highest speed performance available in the PLD market. Lattice
Semiconductor’s E2CMOS circuitry achieves power levels as low
as 75mA typical I which represents a substantial savings in power
CC
when compared to bipolar counterparts. E2 technology offers high
speed (<100ms) erase times providing the ability to reprogram,
reconfigure or test the devices quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20RA10 is a direct parametric compatible CMOS
replacement for the PAL20RA10 device.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. Therefore, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
4
I5
2 28 26
25
I
I7
23
NC GAL20RA10
I 9 Top View 21
I
I 11
19
12 14 16 18
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
DIP
PL 1
I
24 Vcc
I/O/Q
I
I GAL
I 20RA10
I6
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I 18 I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
I I/O/Q
GND 12
13 OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
July 1997
20ra10_02
1

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