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M4A5-256 fiches techniques PDF

Lattice Semiconductor - High Performance E2CMOS In-System Programmable Logic

Numéro de référence M4A5-256
Description High Performance E2CMOS In-System Programmable Logic
Fabricant Lattice Semiconductor 
Logo Lattice Semiconductor 





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M4A5-256 fiche technique
ispMACH4A CPLD Family
High Performance E2CMOS®
In-System Programmable Logic
FEATURES
High-performance, E2CMOS 3.3-V & 5-V CPLD families
Flexible architecture for rapid logic designs
— Excellent First-Time-FitTM and ret feature
— SpeedLockingTM performance for guaranteed xed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
32 to 512 macrocells; 32 to 768 registers
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-FriendlyTM inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Advanced E2CMOS process provides high-performance, cost-effective solutions
Lead-free package options
Lead-
Free
Package
Options
Available!
Publication# ISPM4A Rev: M
Amendment/0
Issue Date: September 2006

PagesPages 30
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