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PDF GAL16LV8C-10LJ Data sheet ( Hoja de datos )
| Número de pieza | GAL16LV8C-10LJ | |
| Descripción | Low Voltage E2CMOS PLD Generic Array Logic | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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GAL16LV8
Low Voltage E2CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices
(GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Functional Block Diagram
I/CLK
I
I
I
I
I
I
I
I
CLK
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
8 OLMC
OE
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/OE
Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time,
provides the highest speed performance available in the PLD
market. The GAL16LV8C can interface with both 3.3V and 5V
signal levels. The GAL16LV8 is manufactured using Lattice
Semiconductor's advanced 3.3V E2CMOS process, which com-
bines CMOS with Electrically Erasable (E2) floating gate technology.
High speed erase times (<100ms) allow the devices to be repro-
grammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 archi-
tecture as its 5V counterpart and supports all architectural features
such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
PLCC
I
I4
I I/CLK Vcc I/O/Q
2 20
18
I/O/Q
I
I6
I
GAL16LV8
Top View
I/O/Q
16 I/O/Q
I/O/Q
I8
14 I/O/Q
9 11 13
I GND I/OE I/O/Q I/O/Q
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
December 1997
16lv8_04
1
1 page  
Specifications GAL16LV8
Registered Mode Logic Diagram
PLCC Package Pinout
1
2128
0 4 8 12 16 20 24 28 PTD
0000
0224
2
0256
0480
3
0512
0736
4
0768
0992
5
1024
1248
6
1280
1504
7
1536
1760
8
1792
2016
9
2191
OLMC
XOR-2048
AC1-2120
OLMC
XOR-2049
AC1-2121
OLMC
XOR-2050
AC1-2122
OLMC
XOR-2051
AC1-2123
OLMC
XOR-2052
AC1-2124
OLMC
XOR-2053
AC1-2125
OLMC
XOR-2054
AC1-2126
OLMC
XOR-2055
AC1-2127
SYN-2192
AC0-2193
19
18
17
16
15
14
13
12
OE 11
5
5 Page 
Specifications GAL16LV8D
AC Switching Characteristics
Over Recommended Operating Conditions
TEST
PARAMETER COND1.
DESCRIPTION
tpd2 A Input or I/O to Combinational Output
tco2 A Clock to Output Delay
tcf3 — Clock to Feedback Delay
tsu — Setup Time, Input or Feedback before Clock↑
th — Hold Time, Input or Feedback after Clock↑
A Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
fmax4
A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
A Maximum Clock Frequency with
No Feedback
twh4
twl4
ten
— Clock Pulse Duration, High
— Clock Pulse Duration, Low
B Input or I/O to Output Enabled
B OE to Output Enabled
tdis C Input or I/O to Output Disabled
C OE to Output Disabled
1) Refer to Switching Test Conditions section.
2) Minimum values for tpd and tco are not 100% tested but established by characterization.
3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
4) Refer to fmax Descriptions section. Characterized but not 100% tested.
COM
COM
-3 -5
UNITS
MIN. MAX. MIN. MAX.
1 3.5 1 5 ns
1 2.5 1 3 ns
— 2 — 2 ns
3 — 4 — ns
0 — 0 — ns
180 — 142.8 — MHz
200 — 166 — MHz
250 — 166 — MHz
2—
2—
— 4.5
— 3.5
3
3
—
—
— 4.5 —
— 3.5 —
—
—
6
5
6
5
ns
ns
ns
ns
ns
ns
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
CI
CI/O
PARAMETER
Input Capacitance
I/O Capacitance
TYPICAL
5
5
UNITS
pF
pF
TEST CONDITIONS
VCC = 3.3V, VI = 0V
VCC = 3.3V, VI/O = 0V
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet GAL16LV8C-10LJ.PDF ] | |
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