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PDF NCP1082 Data sheet ( Hoja de datos )
| Número de pieza | NCP1082 | |
| Descripción | Integrated PoE-PD & DC-DC Converter Controller | |
| Fabricantes | ON Semiconductor | |
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NCP1082
Integrated PoE-PD & DC-DC
Converter Controller with
9 V Auxiliary Supply Support
Introduction
The NCP1082 is a member of ON Semiconductor’s Power over
Ethernet Powered Device (PoE−PD) product family and represents a
robust, flexible and highly integrated solution targeting demanding
Ethernet applications. It combines in a single unit an enhanced
PoE−PD interface fully supporting the IEEE 802.3af specification and
a flexible and configurable DC−DC converter controller.
The NCP1082’s exceptional capabilities enable applications to
smoothly transition from non−PoE to PoE enabled networks by also
supporting power from auxiliary sources such as AC power adapters
and battery supplies, eliminating the need for a second switching
power supply.
ON Semiconductor’s unique manufacturing process and design
enhancements allow the NCP1082 to deliver up to 13 W of regulated
power to support PoE applications according to the IEEE 802.3af
standard. This device leverages the significant cost advantages of
PoE−enabled systems to a broad spectrum of products in markets such
as VoIP phones, wireless LAN access points, security cameras, point
of sales terminals, RFID readers, industrial ethernet devices, etc.
The integrated current mode DC−DC controller facilitates isolated
and non−isolated fly−back, forward and buck converter topologies. It
has all the features necessary for a flexible, robust and highly efficient
design including programmable switching frequency, duty cycle up to
80 percent, slope compensation, and soft start−up.
The NCP1082 is fabricated in a robust high voltage process and
integrates a rugged vertical N−channel DMOS with a low loss current
sense technique suitable for the most demanding environments and
capable of withstanding harsh environments such as hot swap and
cable ESD events.
The NCP1082 complements ON Semiconductor’s ASSP portfolio
in communications and industrial devices and can be combined with
other high−voltage interfacing devices to offer complete solutions to
the communication, industrial and security markets.
http://onsemi.com
1
TSSOP−20 EP
DE SUFFIX
CASE 948AB
NCP1082 = Specific Device Code
XXXX = Date Code
Y = Assembly Location
ZZ = Traceability Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Features
• This is a Pb−Free Device
Powered Device Interface
• Flexible Auxiliary Power Supply Support
• 9 V Front, Rear and Direct Auxiliary Supply
Connections
• Fully Supports IEEE 802.3af Standard
• Regulated Power Output up to 13 W
• Programmable Classification Current
• Adjustable Under Voltage Lock Out
• Programmable Inrush Current Limit
• Programmable Operational Current Limit up to 500 mA
• Over−temperature Protection
• Industrial Temperature Range −40°C to 85°C with Full
Operation up to 150°C Junction Temperature
• 0.6 Ohm Hot−swap Pass−switch with Low Loss
Current Sense Technique
• Vertical N−channel DMOS Pass−switch Offers the
Robustness of Discrete MOSFETs with Integrated
Temperature Control
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 3
1
Publication Order Number:
NCP1082/D
1 page  
NCP1082
Table 1. PIN DESCRIPTIONS
Name
Pin No.
Type
VPORTP 1 Supply
VPORTN1
VPORTN2
6,8
Ground
RTN
7 Ground
ARTN
14 Ground
VDDH
16 Supply
VDDL
17 Supply
CLASS
INRUSH
ILIM1
2
4
5
Input
Input
Input
UVLO
3 Input
GATE
OSC
NC
COMP
15 Output
11 Input
13
18 I/O
FB
CS
SS
AUX
19 Input
12 Input
20 Input
9 Input
TEST
EP
10 Input
Description
Positive input power. Voltage with respect to VPORTN1,2
Negative input power. Connected to the source of the internal pass−switch.
DC−DC controller power return. Connected to the drain of the internal pass−switch. It must
be connected to ARTN. This pin is also the drain of the internal pass−switch.
DC−DC controller ground pin. Must be connected to RTN as a single point ground connection
for improved noise immunity.
Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal
gate driver. VDDH must be bypassed to ARTN with a 1 mF or 2.2 mF ceramic capacitor with
low ESR.
Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be
used to bias an external low−power LED (1 mA max.) connected to ARTN, and can also be
used to add extra biasing current in the external opto−coupler. VDDL must be bypassed to
ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR.
Classification current programming pin. Connect a resistor between CLASS and VPORTN1,2.
Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN1,2.
Operational current limit programming pin. Connect a resistor between ILIM1 and
VPORTN1,2.
DC−DC controller under−voltage lockout input. Voltage with respect to VPORTN1,2. Connect
a resistor−divider from VPORTP to UVLO to VPORTN1,2 to set an external UVLO threshold.
DC−DC controller gate driver output pin.
Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN.
No connect pin, must not be connected.
Output of the internal error amplifier of the DC−DC controller. COMP is pulled−up internally to
VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the
opto−coupler. Voltage with respect to ARTN.
DC−DC controller inverting input of the internal error amplifier. In isolated applications, the pin
should be strapped to ARTN to disable the internal error amplifier.
Current−sense input for the DC−DC controller. Voltage with respect to ARTN.
Soft−start input for the DC−DC controller. A capacitor between SS and ARTN determines the
soft−start timing.
When the pin is pulled up, the IEEE detection mode is disabled and the device can be sup-
plied by an auxiliary supply. Voltage with respect to VPORTN1,2. Connect the pin to the auxili-
ary supply through a resistor divider.
Digital test pin must always be connected to VPORTN1,2.
Exposed pad. Connected to VPORTN1,2 ground.
http://onsemi.com
5
5 Page 
NCP1082
DESCRIPTION OF OPERATION
Powered Device Interface
The PD interface portion of the NCP1082 supports the
IEEE 802.3af defined operating modes: detection signature,
current source classification, inrush and operating current
limits. In order to give more flexibility to the user and also
to keep control of the power dissipation in the NCP1082,
both current limits are configurable. The device enters
operation once its programmable Vuvlo_on threshold is
reached, and operation ceases when the supplied voltage
falls below the Vuvlo_off threshold. Sufficient hysteresis
and Uvlo filter time are provided to avoid false power on/off
cycles due to transient voltage drops on the cable.
Power Mode
When the classification hand−shake is completed, the
PSE and PD devices move into the operating mode.
Under Voltage Lock Out (UVLO)
The NCP1082 incorporates an under voltage lock out
(UVLO) circuit which monitors the input voltage and
determines when to apply power to the DC−DC controller.
To use the default settings for UVLO (see Table 3), the pin
UVLO must be connected to VPORTN1,2. In this case the
signature resistor has to be placed directly between
VPORTP and VPORTN1,2, as shown in Figure 9.
Detection
During the detection phase, the incremental equivalent
resistance seen by the PSE through the cable must be in the
IEEE 802.3af standard specification range (23.75 kW to
26.25 kW) for a PSE voltage from 2.7 V to 10.1 V. In order
to compensate for the non−linear effect of the diode bridge
and satisfy the specification at low PSE voltage, the
NCP1082 presents a suitable impedance in parallel with the
25.5 kW Rdet external resistor connected between VPORTP
and VPORTN. For some types of diodes (especially Schottky
diodes), it may be necessary to adjust this external resistor.
When the Detection_Off level is detected (typically
11.5 V) on VPORTP, the NCP1082 turns on its internal
3.3 V regulator and biasing circuitry in anticipation of the
classification phase as the next step.
Classification
Once the PSE device has detected the PD device, the
classification process begins. In classification, the PD
regulates a constant current source that is set by the external
resistor RCLASS value on the CLASS pin. Figure 8 shows
the schematic overview of the classification block. The
current source is defined as:
Iclass
+
Vbg
Rclass
,
(where Vbg is 1.2
V)
VPORTP
VDDA1
1.2 V
VPORTP
VPORT Rdet
UVLO
VPORTN1,2
NCP1082
Figure 9. Default UVLO Settings
To define the UVLO threshold externally, the UVLO pin
must be connected to the center of an external resistor
divider between VPORTP and VPORTN1,2 as shown in
Figure 10. The series resistance value of the external
resistors must add to 25.5 kW and replaces the internal
signature resistor.
VPORTP
VPORT
R1
R2
UVLO
VPORTN1,2
NCP1082
CLASS
Figure 10. External UVLO Configuration
Rclass
VPORTN1,2
NCP1082
Figure 8. Classification Block Diagram
For a Vuvlo_on desired turn−on voltage threshold, R1 and
R2 can be calculated using the following equations:
R1 ) R2 + Rdet
R2
+
1.2
Vulvo_on
Rdet
When using the external resistor divider, the NCP1082 has
an external reference voltage hysteresis of 15 percent typical.
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11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet NCP1082.PDF ] | |
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