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PDF 54ABT245 Data sheet ( Hoja de datos )
| Número de pieza | 54ABT245 | |
| Descripción | Octal Bidirectional Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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March 1996
54ABT 74ABT245
Octal Bidirectional Transceiver with TRI-STATE Outputs
General Description
The ’ABT245 contains eight non-inverting bidirectional buff-
ers with TRI-STATE outputs and is intended for bus-orient-
ed applications Current sinking capability is 64 mA on both
the A and B ports The Transmit Receive (T R) input deter-
mines the direction of data flow through the bidirectional
transceiver Transmit (active HIGH) enables data from A
ports to B ports Receive (active LOW) enables data from B
ports to A ports The Output Enable input when HIGH dis-
ables both A and B ports by placing them in a High Z condi-
tion
Features
Y Bidirectional non-inverting buffers
Y A and B output sink capability of 64 mA source capa-
bility of 32 mA
Y Guaranteed output skew
Y Guaranteed multiple output switching specifications
Y Output switching specified for both 50 pF and 250 pF
loads
Y Guaranteed simultaneous switching noise level and dy-
namic threshold performance
Y Guaranteed latchup protection
Y High impedance glitch-free bus loading during entire
power up and power down cycle
Y Non-destructive hot insertion capability
Y Disable time is less than enable time to avoid bus
contention
Y Standard Military Drawing (SMD) 5962-9214801
Commercial
Military
Package
Number
Package Description
74ABT245CSC (Note 1)
M20B 20-Lead (0 300 Wide) Molded Small Outline JEDEC
74ABT245CSJ (Note 1)
M20D 20-Lead (0 300 Wide) Molded Small Outline EIAJ
74ABT245CPC
N20B 20-Lead (0 300 Wide) Molded Dual-In-Line
54ABT245J 883 J20A 20-Lead Ceramic Dual-In-Line
74ABT245CMSA (Note 1)
MSA20 20-Lead Molded Shrink Small Outline EIAJ Type II
54ABT245W 883 W20A 20-Lead Cerpak
54ABT245E 883 E20A 20-Lead Ceramic Leadless Chip Carrier Type C
74ABT245CMTC (Notes 1 2)
MTC20 20-Lead Molded Thin Shrink Small Outline JEDEC
Note 1 Devices also available in 13 reel Use suffix e SCX SJX MSAX and MTCX
Note 2 Contact factory for package availability
Logic Symbol
Connection Diagrams
Pin Assignment for DIP
Flatpak SSOP and SOIC
Pin Assignment for LCC
TL F 10945–1
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL F 10945
TL F 10945 – 5
RRD-B30M36 Printed in U S A
TL F 10945 – 3
http www national com
1 page  
Extended AC Electrical Characteristics (SOIC package)
74ABT
74ABT
74ABT
Symbol
Parameter
b40 C to a85 C
VCC e 4 5V – 5 5V
CL e 50 pF
8 Outputs Switching
(Note 4)
TA e b40 C to a85 C
VCC e 4 5V – 5 5V
CL e 250 pF
1 Output Switching
(Note 5)
TA e b40 C to a85 C
VCC e 4 5V – 5 5V
CL e 250 pF
8 Outputs Switching
(Note 6)
Units
Min Typ
Max
Min
Max
Min
Max
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Disable Time
15
15
10
10
65 25
65 25
75
75
65
56
(Note 7)
25 95
2 5 11 0
(Note 7)
ns
ns
Note 4 This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all low-to-high high-
to-low etc )
Note 5 This specification is guaranteed but not tested The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load This specification pertains to single output switching only
Note 6 This specification is guaranteed but not tested The limits represent propagation delays for all paths described switching in phase (i e all low-to-high high-
to-low etc ) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 7 The TRI-STATE delays are dominated by the RC network (500X 250 pF) on the output and have been excluded from the datasheet
Skew (SOIC package)
74ABT
74ABT
Symbol
Parameter
TA e b40 C to a85 C
VCC e 4 5V – 5 5V
CL e 50 pF
8 Outputs Switching
(Note 3)
TA e b40 C to a85 C
VCC e 4 5V – 5 5V
CL e 250 pF
8 Outputs Switching
(Note 4)
Units
Max Max
tOSHL
(Note 1)
Pin to Pin Skew
HL Transitions
13
2 3 ns
tOSLH
(Note 1)
Pin to Pin Skew
LH Transitions
10
1 8 ns
tPS
(Note 5)
Duty Cycle
LH–HL Skew
20
3 5 ns
tOST
(Note 1)
Pin to Pin Skew
LH HL Transitions
20
3 5 ns
tPV
(Note 2)
Device to Device Skew
LH HL Transitions
20
3 5 ns
Note 1 Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device The
specification applies to any outputs switching HIGH to LOW (tOSHL) LOW to HIGH (tOSLH) or any combination switching LOW to HIGH and or HIGH to LOW
(tOST) The specification is guaranteed but not tested
Note 2 Propagation delay variation for a given set of conditions (i e temperature and VCC) from device to device This specification is guaranteed but not tested
Note 3 This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all low-to-high high-
to-low etc )
Note 4 These specifications guaranteed but not tested The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors
in the standard AC load
Note 5 This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin It is measured across all the
outputs (drivers) on the same chip the worst (largest delta) number is the guaranteed specification This specification is guaranteed but not tested
Capacitance
Symbol
Parameter
Typ
CIN
Input Capacitance
50
CI O (Note 1)
I O Capacitance
11 0
Note 1 CI O is measured at frequency f e 1 MHz per MIL-STD-883B Method 3012
Units
pF
pF
Conditions
TA e 25 C
VCC e 0V (OE T R)
VCC e 5 0V (An Bn)
5 http www national com
5 Page 
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
20-Lead Small Outline Integrated Circuit JEDEC (S)
NS Package Number M20B
11
http www national com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet 54ABT245.PDF ] | |
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