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Allegro MicroSystems - DMOS Microstepping Driver

Numéro de référence A3983
Description DMOS Microstepping Driver
Fabricant Allegro MicroSystems 
Logo Allegro MicroSystems 





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A3983 fiche technique
A3983
DMOS Microstepping Driver with Translator
Features and Benefits
Low RDS(ON) outputs
Automatic current decay mode detection/selection
Mixed and Slow current decay modes
Synchronous rectification for low power dissipation
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
Package: 24-pin TSSOP with exposed thermal pad
(suffix LP)
Not to scale
Description
The A3983 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, quarter-, and eighth-step
modes, with an output drive capacity of up to 35 V and ±2 A.
The A3983 includes a fixed off-time current regulator which
has the ability to operate in Slow or Mixed decay modes.
The translator is the key to the easy implementation of the
A3983. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A3983 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
The chopping control in the A3983 automatically selects the
current decay mode (Slow or Mixed). When a signal occurs at
the STEP input pin, the A3983 determines if that step results
in a higher or lower current in each of the motor phases. If
the change is to a higher current, then the decay mode is set to
Slow decay. If the change is to a lower current, then the current
decay is set to Mixed (set initially to a fast decay for a period
amounting to 31.25% of the fixed off-time, then to a slow
decay for the remainder of the off-time). This current decay
Continued on the next page…
Functional Block Diagram
VREG
0.22 μF
ROSC
0.1 μF
CP1 CP2
VDD
Current
Regulator
OSC
Charge
Pump
VCP
REF
DAC
STEP
DIR
RESET
MS1
MS2
Translator
ENABLE
SLEEP
DAC
PWM Latch
Blanking
Mixed Decay
Control
Logic
PWM Latch
Blanking
Mixed Decay
DMOS Full Bridge
Gate
Drive
DMOS Full Bridge
VBB1
OUT1A
OUT1B
SENSE1
VBB2
OUT2A
OUT2B
SENSE2
VREF
0.1 μF
RS1
RS2
26184.29D

PagesPages 13
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