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PDF M95640-DF Data sheet ( Hoja de datos )
| Número de pieza | M95640-DF | |
| Descripción | 64-Kbit serial SPI bus EEPROM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M95640-W M95640-R
M95640-DF
64-Kbit serial SPI bus EEPROM with high-speed clock
Features
■ Compatible with the Serial Peripheral Interface
(SPI) bus
■ Memory array
– 64 Kb (8 Kbytes) of EEPROM
– Page size: 32 bytes
■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
■ Additional Write lockable page (Identification
page)
■ Write Protect: quarter, half or whole memory
array
■ High-speed clock: 20 MHz
■ Single supply voltage:
– 2.5 V to 5.5 V for M95640-W
– 1.8 V to 5.5 V for M95640-R
– 1.7 V to 5.5 V for M95640-DF
■ Operating temperature range: from -40°C up to
+85°C
■ Enhanced ESD protection
■ More than 4 million Write cycles
■ More than 200-year data retention
■ Packages
– RoHS compliant and halogen-free
(ECOPACK®)
Datasheet − production data
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
UFDFPN8 (MC)
2 x 3 mm (MLP8)
WLCSP (CT)
February 2013
This is information on a product in full production.
Doc ID 16877 Rev 17
1/49
www.st.com
1
1 page  
M95640-W M95640-R M95640-DF
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
8-bump thin WLCSP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 41
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 42
UFDFPN8 (MLP8) - 8-lead ultra thin fine pitch dual flat no lead, package outline . . . . . . . 43
Thin WLCSP 8-bump wafer-length chip-scale package outline . . . . . . . . . . . . . . . . . . . . . 44
Thin WLCSP 8-bump wafer-length chip-scale package
recommended land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 16877 Rev 17
5/49
5 Page 
M95640-W M95640-R M95640-DF
4 Connecting to the SPI bus
Connecting to the SPI bus
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 5. Bus master and memory devices on the SPI bus
R
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDO
SDI
SCK
SPI Bus Master
CS3 CS2 CS1
R
VSS
VCC
CQD
VCC
VSS
CQD
VCC
VSS
C Q D VCC
VSS
SPI Memory
Device
R
SPI Memory R
Device
SPI Memory
Device
S W HOLD
S W HOLD S W HOLD
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 5 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 5) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
tSHCH requirement is met. The typical value of R is 100 kΩ..
Doc ID 16877 Rev 17
11/49
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M95640-DF.PDF ] | |
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