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PDF HD66760 Data sheet ( Hoja de datos )
| Número de pieza | HD66760 | |
| Descripción | 104 x 80-dot Graphics LCD Controller/Driver | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HD66760 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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HD66760
104 × 80-dot Graphics LCD Controller/Driver for 256 Colors
ADE-207-335A(Z)
Rev.2.0
September 2001
Description
The HD66760, color-graphics LCD controller and driver LSI, displays 104-by-80-dot graphics for 256 STN
colors. The HD66760's bit-operation functions and a 16-bit high-speed bus interface enable efficient data
transfer and high-speed rewriting of data to the graphics RAM.
The HD66760 has various functions for reducing the power consumption of an LCD system, such as low-
voltage operation of 2.2 V/min., a step-up circuit to generate a maximum of six-times the LCD drive voltage
from the supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleeder-
resistors. Combining these hardware functions with software functions, such as a partial display with low-
duty drive and standby and sleep modes, allows precise power control. The HD66760 is suitable for any mid-
sized or small portable battery-driven product requiring long-term driving capabilities, such as digital cellular
phones supporting a WWW browser, bidirectional pagers, and small PDAs.
Features
• 104 × 80-dot graphics display LCD controller/driver for 256 STN colors
• Display mode change between 256 colors (8 bits per pixel) and four colors (2-bit per pixel)
• 16/8-bit high-speed bus interface
• I2C bus interface
• Clock synchronized serial interface
• Bit-operation functions for graphics processing:
Write-data mask function in bit units
Swap function of upper and lower bytes
Logical operation in pixel unit and conditional write function
• Various color-display control functions:
256 of the 4,096 possible colors can be displayed at the same time (grayscale palette incorporated)
Vertical scroll display function in raster-row units
Color window cursor display supported by hardware
• Low-power operation supports:
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specification.
1 page  
HD66760 Pad Arrangement
HD66760
• Chip size: 14.4 mm × 3.1 mm
• Chip thickness: 550 µm (typ.)
• PAD coordinates: PAD center
• Coordinate origin: Chip center
• Au bump size (pin number is shown
in the blacket)
(1) 80 µm × 80 µm
dummy1 (500), dummy31 (121),
dummy32 (172) and dummy33 (449)
from C6 + (1) to dummy30 (112)
(2) 35 µm × 80 µm
from SEG294 (173) to SEG19 (448)
(3) 80 µm × 35 µm
from COM49 (122) to SEG295 (171)
from SEG18 (450) to COM9 (499)
(4) 45 µm × 80 µm
from COM8 (501) to COM1 (508)
from COM41 (113) to COM48 (120)
• Au bump pitch: Refer PAD coordinate
• Au bump height: 15 µm (typ.)
No.500
dummy1
COM8
COM1
C6+
C6-
C5+
C5-
C4+
C4-
C3+
C3-
C2+
C2-
C1+
C1-
GNDDUM1
VLOUT
VLOUT
VLOUT
VLPS
VLPS
VLPS
VL1REF
VLREF
V1REF
V1OUT
V2OUT
V3OUT
V4OUT
V5OUT
Vci
Vci
Vci
Vci
Vci
dummy2
dummy3
No.501
No.508
No.1
No.2
No.450
No.448
No.449
dummy33
SEG19
SEG20
dummy14
dummy15
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
GND
GND
GND
GND
GND
GND
GND
VTEST
VREG
VSW1
VSW2
GNDDUM2
TEST
OPOFF
VccDUM1
RESET*
CS*
RS
GNDDUM3
VccDUM2
IM0/ID
GNDDUM4
IM1
IM2
RW/RD*/SDA
E/WR*/SCL
GNDDUM5
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
OSC1
OSC2
dummy16
dummy17
HD66760
(Top view)
Y
X
dummy29
dummy30
COM41
COM48
dummy31
No.121
No.120
No.122
No.173
No.171
SEG293
SEG294
dummy32
No.172
5
5 Page 
Block Function Description
HD66760
System Interface
The HD66760 has four high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16-bit/8-bit
bus, an I2C bus interface and a clock synchronized serial interface. The interface mode is selected by the IM2-
0 pins.
The HD66760 has three 16-bit registers: an index register (IR), a write data register (WDR), and a read data
register (RDR). The IR stores index information from the control registers and the GRAM. The WDR
temporarily stores data to be written into control registers and the GRAM, and the RDR temporarily stores
data read from the GRAM. Data written into the GRAM from the MPU is first written into the WDR and then
is automatically written into the GRAM by internal operation. Data is read through the RDR when reading
from the GRAM, and the first read data is invalid and the second and the following data are normal. When a
logic operation is performed inside of the HD66760 by using the display data set in the GRAM and the data
written from the MPU, the data read through the RDR is used. Accordingly, the MPU does not need to read
data twice nor to fetch the read data into the MPU. This enables high-speed processing.
Execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written in
succession.
Table 2 Register Selection
80-series Bus
WR Bits RD Bits
01
10
01
10
68- series
Bus
R/W Bits
0
1
0
1
RS Bits
0
0
1
1
Operations
Writes indexes into IR
Reads internal status
Writes into control registers and GRAM through WDR
Reads from GRAM through RDR
Bit Operation
The HD66760 supports the following functions: a swap function that writes the data written from the MPU
into the GRAM by reversing the display position vertically in byte units, a write data mask function that
selects and writes data into the GRAM in bit units, and a logic operation function that performs logic
operations or conditional determination on the display data set in the GRAM and writes into the GRAM. With
the 16-bit bus interface, these functions can greatly reduce the processing loads of the MPU graphics software
and can rewrite the display data in the GRAM at high speed. For details, see the Graphics Operation Function
section.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD66760.PDF ] | |
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