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PDF RDA5815 Data sheet ( Hoja de datos )

Número de pieza RDA5815
Descripción Fully Integrated Satellite receiver
Fabricantes RDA 
Logotipo RDA Logotipo

RDA5815 datasheet pdf


1. - Fully Integrated Satellite receiver






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RDA Microelectronics, Inc.
RDA5815-Fully Integrated Satellite receiver for DVB-S , DVB-S2 & ABS-SMMDS
DATA SHEET
RDA5815
Fully Integrated, Direct Down-Conversion Satellite
Receiver for DVB-S,DVB-S2&ABS-S,MMDS
______
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole
or in part without prior written permission of RDA.

1 page




RDA5815 pdf
RDA Microelectronics, Inc.
RDA5815-Fully Integrated Satellite receiver for DVB-S , DVB-S2 & ABS-S,MMDS
Baseband LPF
The bansband low-pass filter is designed to have variable cut-off frequency. The bandwidth of the LPF is
selectable from 4MHz to 40MHz with 1MHz step. The DC-offset calibration can be carried out controlled by the
interface. A innovative technique ensure the filters bandwidth variety within 5%.
Reference Oscillator
The oscillator is on-chip integrated and both the crystal and crystal oscillator are supported. The 27MHz is
recommended. The centre oscillation frequency can be adjusted accurately with the XAFC pin (optional
function).
VCO
The receiver integrates two VCOs which ensure covering the full receiving frequency from 250MHz to 2300MHz.
The two VCOs can be switched between each other with relevant register and the VCOs band is programmed
using 2-wire (I2C) interface. The first VCO oscillates from 2100MHz to 2918MHz, the second oscillates from
2818MHz to 4350MHz. After divided by two or four, lo signal from 900MHz to 2250MHz can be obtained.
LO frequency
Used VCO
Divider
950MHz~1074MHz
VCO2
4
1075MHz~1434MHz
VCO1
2
1435MHz~2150MHz
VCO2
2
PLL
The fractional-N frequency synthesizer use 27MHz reference as default. The dividers, loop filters,
phase&frequency detector, charge pump are all integrated on chip.
Baseband Output Amplifier
Class-AB architecture is selected for the output buffer, this makes it more flexible to the next Baseband solutions
input load. The gain of this stage can also be programmed with interface to farther increase the receiver
dynamic.
XOUT Output
The XOUT pin can supply the reference clock for baseband chip, which is controlled by the XOUT_EN pin and the
XDIV2_EN pin. The XOUT pin sends out signal when XOUT_EN is Vdd, and doesnt send out signal when XOUT_EN is GND.
The output frequency is equal to xtal frequency when XDIV2_EN is GND, and is equal to (xtal frequency)/2 when
XDIV2_EN is Vdd.
I2C interface
The interface is the control unit of all the analog blocks, it is provided for configuration and monitoring all internal
registers, the I2C bus consists of two wires: serial clock line (SCL) and serial data line (SDA). The LNAs gain,
AGC, baseband LPFs bandwidth, VCOs and crystal oscillators current, VCOs oscillation frequency are all
controlled by the 2-wire interface.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole
or in part without prior written permission of RDA.
3

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RDA5815 arduino
RDA Microelectronics, Inc.
RDA5815-Fully Integrated Satellite receiver for DVB-S , DVB-S2 & ABS-S,MMDS
conversion gain
Maximum voltage
conversion gain
Voltage conversion gain
step
Matched input resistance
Power up setting time
Input reflection
coefficient
Gv(max)
Gv(step)
RIN
PUST
S11
(3.3 V)
AGCIN set to minimum
(0.1V)
After matching
After matching
82
0.2
75
1
-8 -7
dB
dB
Ω
ms
dB
Table 5 Frequency Synthesizer Characteristics
(VDD = 3 to 3.6 V, TA = -25 to 85 °C, unless otherwise specified)
SYMBOL
tSW
fRFLO
PN1
PN2
PN3
PN4
DESCRIPTION
RX Switch on time
synthesizer frequency
Phase noise
CONDITIONS
Δf=1kHz
Δf=10kHz
Δf=100kHz
Δf=1MHz
MIN
900
-100
-110
-138
TYP
200
-85
-95
-105
-133
MAX
2250
-75
-90
-100
-130
UNIT
us
MHz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Table 6 Baseband LPF and Output Amplifier Characteristics
Parameter
3 dB baseband filter
bandwidth
Cutoff frequency accuracy
at -3dB
LPF 2fc attenuation
Flatness
Group delay
Maximum differential
output voltage
Output common mode
voltage
Differential Output offset
voltage
IQ output impedance
Output Amplifier minimum
load impedance
Output Anplifier maximum
Load capacitance
SYMBOL
BBF(3dB)
FC
LPF ATT1
FLTN
Td(g)
CONDITIONS MIN
4
TYP MAX UNIT
40 MHz
+/-5 %
25
Clipping level
0.5
2
0.9*VDD
1
dB
dBpp
ps
Vpp
0.3*VDD 0.5*VDD 0.6*VDD V
30 mV
25 45 55 Ω
1K Ω
10 pF
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole
or in part without prior written permission of RDA.
10

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