R5F562T6BDFF Datasheet PDF ( Pinout ) - 100-MHz 32-bit RX MCUs

R5F562T6BDFF Datasheet PDF - Renesas

Part Number	*R5F562T6BDFF*
Description	100-MHz 32-bit RX MCUs
Manufacturers	Renesas
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DATASHEET

RX62T Group, RX62G Group

Renesas MCUs

R01DS0096EJ0200

100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC (3 S/H circuits, double data

Rev.2.00

Jan 10, 2014

capable of simultaneous 7-ch. sampling, 100-MHz PWM (two three-phase complementary

channels and four single-phase complementary channels or three three-phase

complementary channels and one single-phase complementary channel)

Features

■ 32-bit RX CPU core

 Max. operating frequency: 100 MHz

Capable of 165 DMIPS in operation at 100 MHz

 Single precision 32-bit IEEE-754 floating point

 Accumulator handles 64-bit results (for a single

instruction) from 32- × 32-bit operations

 Multiplication and division unit handles 32- × 32-bit

operations (multiplication instructions take one CPU

clock cycle)

 Fast interrupt

 Divider (fastest instruction execution takes two CPU

clock cycles)

 Fast interrupt

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions: Ultra-compact code

 Supports the memory protection unit (MPU)

 Background JTAG debugging plus high-speed tracing

■ Operating voltage

 Single 3.3- or 5-V supply; 5-V analog supply is possible

with 3.3-V products

■ Low-power design and architecture

 Four low-power modes

■ On-chip main flash memory, no wait states

 100-MHz operation, 10-ns read cycle

 No wait states for reading at full CPU speed

 64-Kbyte/128-Kbyte/256-Kbyte capacities

 For instructions and operands

 User code programmable via the SCI or JTAG

■ On-chip data flash memory

 Max. 32 Kbytes, reprogrammable up to 30,000 times

 Erasing and programming impose no load on the CPU.

■ On-chip SRAM, no wait states

 8-Kbyte/16-Kbyte SRAM

 For instructions and operands

■ DMA

 DTC: The single unit is capable of transfer on multiple

channels

■ Reset and supply management

 Power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

■ Clock functions

 External crystal oscillator or internal PLL for operation at

8 to 12.5 MHz

 Internal 125-kHz LOCO for the IWDT

 Detection of main oscillator stoppage (for IEC 60730

compliance)

■ Independent watchdog timer

(for IEC60730compliance)

 125-kHz LOCO clock operation

 Software is incapable of stopping the robust WDT.

R01DS0096EJ0200 Rev.2.00

Jan 10, 2014

PLQP0112JA-A 20×20mm, 0.65mm pitch

PLQP0100KB-A 14×14mm, 0.5mm pitch

PLQP0080JA-A 14×14mm, 0.65mm pitch

PLQP0064KB-A 10×10mm, 0.5mm pitch

PLQP0064GA-A 14x14 mm, 0.8mm pitch

■ Up to 7 communications interfaces

 1: CAN (compliant with ISO11898-1), incorporating 32

mailboxes

 3: SCIs, with asynchronous mode (incorporating noise

cancellation), clock-synchronous mode, and smart-card

interface mode

 1: I2C bus interface, capable of SMBus operation

 1: RSPI

 1: LIN

■ Up to 16 16-bit timers

 8: 16-bit MTU3: 100-MHz operation, input capture,

output compare, two three-phase complementary PWM

output channels, complementary PWM imposing no load

on the CPU, phase-counting mode

 4: 16-bit GPT: 100-MHz operation, input capture, output

compare, four complementary single-phase PWM output

channels, or one three-phase complementary PWM

output channel and one single-phase complementary

PWM output channel, complementary PWM imposing no

load on the CPU, operation linked with comparator (for

counting and control of PWM-signal negation), detection

of abnormal oscillation frequencies (for IEC 60730

compliance)

 4: 16-bit CMT

■ Generation of delays in PWM waveforms (only for

the RX62G Group)

 The timing with which signals on the 16-bit GPT PWM

output pin rise and fall can be controlled with an accuracy

of up to 312 ps (in operation at 100 MHz).

■ Three A/D converter units for 1-MHz operation,

for a total of 20 channels

 Three units are capable of simultaneous sampling on

seven channels

 Self diagnosis (for IEC60730 compliance)

 8: Two 12-bit ADC units: three sample-and-hold circuits,

double data registers, amplifier, comparator

 12: Single 10-bit ADC unit

■ CRC (cyclic redundancy check) calculation unit

 Monitoring of data being transferred (for IEC 60730

compliance)

 Monitoring of data in memory (for IEC 60730

compliance)

■ Up to 61 input–output ports and up to 21 input-only

ports

 PORT registers: Monitoring of output ports (for IEC

60730 compliance)

■ Operating temp. range

 –40C to +85C

 –40C to +105C

Page 1 of 134

Under development Preliminary document

Specifications in this document are tentative and subject to change.

RX62T Group, RX62G Group

1. Overview

Table 1.1

Outline of Specifications (4 / 5)

Classification

Communications

A/D converter

Module/Function

CAN module (CAN)

(as an optional

function)

Serial peripheral

interface (RSPI)

LIN module (LIN)

12-bit A/D converter

(S12ADA)

 1 channel

 32 mailboxes

Description

 1 unit

 RSPI transfer facility

Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),

and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

 Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

or to 20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with each

frame having up to 32 bits)

 Buffered structure

 Double buffers for both transmission and reception

 1 channel (LIN master)

 Supports revisions 1.3, 2.0, and 2.1 of the LIN protocol

 12 bits (2 units x 4 channels)

 12-bit resolution

 Conversion time:

1.0 s per channel (in operation with A/D conversion clock ADCLK at 50 MHz) for AVCC

= 4.0 to 5.5 V

2.0 s per channel (in operation with A/D conversion clock ADCLK at 25 MHz) for

AVCC0 = 3.0 to 3.6 V

 Two basic operating modes

Single mode and scan mode

 Scan mode

One-cycle scan mode

Continuous scan mode

2-channel scan mode (Input ports of the A/D unit are divided into two groups in this

mode, and the activation sources are separately selectable for each group.)

 Sample-and-hold function

A common sample-and-hold circuit for both units is included.

Additionally, sample-and-hold circuit for each unit is included. (three channels per unit)

 A/D-conversion register settings for each input pin.

 Two registers for the result of conversion are provided for a single analog input pin of

each unit (AN000 and AN100).

 Three ways to start A/D conversion

Conversion can be started by software, a conversion start trigger from a timer (MTU3 or

GPT), or an external trigger signal.

 Functionality for 8- or 10-bit precision output

Right-shifting of the results of conversion for output by two or four bits is selectable.

 Self-diagnostic function

The self-diagnostic function internally generates three analog input voltages (VREFL0,

VREFH0 x 1/2, VREFH0).

 Amplification of input signals by a programmable gain amplifier (three channels per unit)

Amplification rate: 2.0-, 2.5-, 3.077-, 3.636-, 4.0-, 4.444-, 5.0-, 5.714-, 6.667-, 10.0-, or

13.333-times amplification (a total of 11 steps)

 Window comparators (three channels per unit)

R01DS0096EJ0200 Rev.2.00

Jan 10, 2014

Page 5 of 134

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R5F562T6BDFF Datasheet PDF - Renesas

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