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Z8030 fiches techniques PDF

Zilog - Communications Controller

Numéro de référence Z8030
Description Communications Controller
Fabricant Zilog 
Logo Zilog 





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Z8030 fiche technique
Zilog
Z8030 Z8000®
Z-SCC Serial
Communications Controller
Product
Specification
Features
General
Description
• Two independent, 0 to 1.5M bit/second, full-
duplex channels, each with a separate crystal
OSCillator, baud rate generator, and Digital
Phase-Locked Loop for clock recovery.
• Multi-protocol operation under program
control; programmable for NRZ, NRZI, or
FM data encoding.
• Asynchronous mode with five to eight bits
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detection and generation; parity,
overrun, and framing error detection.
• Synchronous mode with internal or external
character synchronization on one or two
The Z8030 Z-SCC Serial Communications
Controller is a dual-channel, multi-protocol
data communications peripheral designed for
use with the Zilog Z-Bus. The Z-SCC functions
as a serial-to-parallel, parallel-to-serial con-
verter/controller. The Z-SCC can be software-
configured to satisfy a wide variety of serial
April 1985
synchronous characters and CRC genera-
tion and checking with CRC-16 or
CRC-CCITT preset to either Is or Os.
• SDLC/HDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handling, abort
generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.
• Local Loopback and Auto Echo modes.
• 1.544M bit/second Tl digital trunk compatible
version available.
communications applications. The device con-
tains a variety of new, sophisticated internal
functions including on-chip baud rate
generators, Digital Phase-Locked Loops, and
crystal oscillators that dramatically reduce the
need for external logic.
2016-001,002
ADDRESS'
DATA BUS
AD,
TxDA
} SERIAL
AD, RIlOA _ _ DATA
AD, TRxCA ........-} CHANNEL
AD, RTxCA .--- CLOCKS
AD,
AD, CHANNEL
AD, CONTROLS
FOR MODEM,
ADo DMA,OR
As OTHER
OS
R/W
es,
} SERIAL
_ _ DATA
esc
INT
INTACK
lEI
lEO
-\IRTxes
._...._...
I\
CHANNEL
CLOCKS
SYNCe
WIREOB
DTR/REQB
RlSB
CHANNEL
CONTROLS
FDOMRAM,OORDEM,
Z8030 else __ OTHER
z·scc DeDS
CH·A
CH·B
ttt
+5V GND PCLK
Figure I. Pin Funcllons
AD,
AD,
AD,
AD,
iNT
lEO
lEi
INTACK
+sv
WIREQA
SYNCA
RheA
RIlOA
TRxCA
hDA
OTR/REQA
RlSA
elSA
DeCA
PClK
ADO
39 AD,
38 AD,
37 AD,
36 OS
35 As
34 RIW
Z8030
z·scc
11
33
32
31
30
eso
es,
GND
W/REoe
12 29 SYNCe
"13 RTxCB
37 RKOB
26 TRlleB
16 25 1)(D8
24 DTRIREQB
18 23 Rlse
19 22 elSS
21 DC De
Figure 2. 40-pin Dual-In-Line Package (DIP).
Pin Assignments
631

PagesPages 22
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