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PDF AD9655 Data sheet ( Hoja de datos )
| Número de pieza | AD9655 | |
| Descripción | 1.8V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Dual, 16-Bit, 125 MSPS Serial LVDS,
1.8 V Analog-to-Digital Converter
AD9655
FEATURES
1.8 V supply operation
Low power: approximately 150 mW/channel at 125 MSPS,
2 V p-p input range (typical)
SNR/SFDR at 69.5 MHz
77.5 dBFS/88 dBc, 2.0 V p-p input range (typical)
79.3 dBFS/84 dBc, 2.8 V p-p input range (typical)
Linearity
DNL = ±0.7 LSB; INL = ±4.0 LSB (typical, 2.0 V p-p input span)
DNL = ±0.7 LSB; INL = ±3.4 LSB (typical, 2.8 V p-p input span)
Serial LVDS, two data lanes per ADC channel
500 MHz full power analog bandwidth
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Clock divider
Programmable output clock and data alignment
Standby mode
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging and ultrasound
Radar/LIDAR
GENERAL DESCRIPTION
The AD9655 is a dual, 16-bit, 125 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and an LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. External reference or driver components are not
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO)
for capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
VINA+
VINA–
VCM
VINB+
VINB–
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
AD9655
16-BIT
PIPELINE
ADC
16-BIT
PIPELINE
ADC
REFERENCE
16
16
16
16
SERIAL PORT
INTERFACE
1 TO 8
CLOCK DIVIDER
D0A+
D0A–
D1A+
D1A–
D0B+
D0B–
D1B+
D1B–
DCO+
DCO–
FCO+
FCO–
SCLK/ SDIO/ CSB
DFS PDWN
CLK+ CLK–
Figure 1.
Individual channel power-down is supported. The AD9655
typically consumes less than 2 mW in serial port interface (SPI)
power-down mode. The available digital test pat-terns include
built-in deterministic and pseudorandom patterns, along with
custom user-defined test patterns entered via the SPI.
The AD9655 is available in an RoHS-compliant, 32-lead LFCSP.
It is specified over the industrial temperature range of −40°C to
+85°C. This device is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint.
Two ADCs are contained in a small, space-saving package.
2. Pin Compatible.
The AD9655 is pin compatible to the AD9645 14-bit and
AD9635 12-bit dual ADCs.
3. Ease of Use.
A DCO operates at frequencies of up to 500 MHz and
supports double data rate (DDR) operation.
4. User Flexibility.
The SPI control offers a wide range of flexible features to
meet specific system requirements.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9655
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p full-scale differential input mode, VREF = 1.0 V, AIN = −1.0 dBFS, 125 MSPS, unless otherwise noted.
Table 3.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD HARMONIC)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 69.5 MHz
fIN = 100.5 MHz
fIN = 139.5 MHz
fIN = 301 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 100.1 MHz, fIN2 = 102.1 MHz
CROSSTALK2
CROSSTALK (OVERRANGE CONDITION)3
ANALOG INPUT BANDWIDTH, FULL POWER
Temperature Min Typ Max Unit
25°C
25°C
25°C
25°C
25°C
25°C
77.9 dBFS
77.9 dBFS
77.5 dBFS
76.6 dBFS
75.6 dBFS
71.0 dBFS
25°C
25°C
25°C
25°C
25°C
25°C
77.5 dBFS
77.1 dBFS
77.1 dBFS
76.5 dBFS
75.2 dBFS
68.0 dBFS
25°C
25°C
25°C
25°C
25°C
25°C
12.6 Bits
12.5 Bits
12.5 Bits
12.4 Bits
12.2 Bits
11 Bits
25°C
25°C
25°C
25°C
25°C
25°C
88 dBc
86 dBc
88 dBc
91 dBc
85 dBc
70 dBc
25°C
25°C
25°C
25°C
25°C
25°C
−88 dBc
−86 dBc
−88 dBc
−91 dBc
−85 dBc
−70 dBc
25°C
25°C
25°C
25°C
25°C
25°C
−95 dBc
−99 dBc
−92 dBc
−91 dBc
−89 dBc
−80 dBc
25°C
90 dBc
25°C
−104
dB
25°C
−100
dB
25°C
500 MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Crosstalk is measured at 69.5 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. Measurements are taken using a less dense
board to demonstrate the AD9655 crosstalk performance, not board limitations.
3 Overrange condition is specified as being 3 dB above the full-scale input range.
Rev. 0 | Page 5 of 37
5 Page 
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9655
AVDD 1
CLK+ 2
CLK– 3
SDIO/PDWN 4
SCLK/DFS 5
DRVDD 6
D1B– 7
D1B+ 8
AD9655
TOP VIEW
(Not to Scale)
24 AVDD
23 RBIAS
22 VCM
21 VREF
20 CSB
19 DRVDD
18 D0A+
17 D0A–
NOTES
1. THE EXPOSED PAD IS THE ONLY GROUND CONNECTION
ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND
OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT
DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 4. Pin Configuration, Top View
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
0, Exposed Pad
AGND,
Exposed Pad
Exposed Pad. The exposed pad is the only ground connection on the chip. It must be soldered to the
analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical
strength benefits.
1, 24, 25, 28, 29, 32 AVDD
1.8 V Supply Pins for the ADC Core Domain.
2, 3
CLK+, CLK−
Differential Encode Clock. These pins are PECL-, LVDS-, or 1.8 V CMOS-compatible inputs.
4 SDIO/PDWN SPI Data Input/Output (SDIO). This pin is a bidirectional SPI data input/output with a 31 kΩ internal
pull-down resistor.
Non-SPI Mode Power-Down (PDWN). This pin provides static control of chip power-down, and has a 31 kΩ
internal pull-down resistor.
5
SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). This pin has a 30 kΩ internal pull-down resistor.
Non-SPI Mode Data Format Select (DFS). This provides static control of the data output format. This
pin has a 30 kΩ internal pull-down resistor. Pull DFS high for a twos complement output; pull DFS
low for an offset binary output.
6, 19
DRVDD
1.8 V Supply Pins for Output Driver Domain.
7, 8 D1B−, D1B+ Channel B Lane 1 Digital Outputs.
9, 10 D0B−, D0B+ Channel B Lane 0 Digital Outputs.
11, 12
DCO−, DCO+ Data Clock Outputs.
13, 14
FCO−, FCO+ Frame Clock Outputs.
15, 16
D1A−, D1A+ Channel A Lane 1 Digital Outputs.
17, 18
D0A−, D0A+ Channel A Lane 0 Digital Outputs.
20 CSB SPI Chip Select. Active low enable; this pin has a 15 kΩ internal pull-up resistor.
21
VREF
1.0 V to 1.4 V Voltage Reference Output. Bypass this pin to ground with a 1.0 µF capacitor in parallel
with a 0.1 µF capacitor; this pin internally provides reference voltage to the ADC. This pin can be
disabled via Register 0x114 if external VREF is desired.
22
VCM
Analog Output Voltage at Mid AVDD Supply. Bypass this pin to ground with a 0.1 µF capacitor; this
pin can be used to set the common mode of the analog inputs externally.
23
RBIAS
Sets Analog Current Bias. Connect this pin to a 10.0 kΩ (1% tolerance) resistor to ground.
26, 27
VINA−, VINA+ Channel A ADC Analog Inputs.
30, 31
VINB+, VINB− Channel B ADC Analog Inputs.
Rev. 0 | Page 11 of 37
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9655.PDF ] | |
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