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PDF N133IB-L01 Data sheet ( Hoja de datos )
| Número de pieza | N133IB-L01 | |
| Descripción | TFT LCD Module | |
| Fabricantes | CMI MEI | |
| Logotipo |  |
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Doc No.:
Issued Date: Mar. 27, 2008
Model No.: N133IB - L01
Tentative
TFT LCD Tentative Specification
MODEL NO.: N133IB - L01
Customer:
Approved by:
Note:
2008-04-02 PMMD
17:18:32 CST Director
cs_lee(
/56510/44926)
Director Accept
1 / 26
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Global LCD Panel Exchange Center
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Doc No.:
Issued Date: Mar. 27, 2008
Model No.: N133IB - L01
Tentative
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item
Storage Temperature
Operating Ambient Temperature
Shock (Non-Operating)
Vibration (Non-Operating)
Symbol
TST
TOP
SNOP
VNOP
Value
Min. Max.
-20 +60
0 +50
- 200/2
- 1.5
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Unit
ºC
ºC
G/ms
G
Note
(1)
(1), (2)
(3), (5)
(4), (5)
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
10 Storage Range
-40 -20
0 20 40 60 80
Temperature (ºC)
Note (2) The temperature of panel surface should be 0 ºC Min. and 60 ºC Max.
Note (3) 1 time for ± X, ± Y, ± Z. for Condition (200G / 2ms) is half Sine Wave,
Note (4) 10 ~ 200 Hz, 0.5 Hr / Cycle, 1 cycles for each X, Y, Z axis.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough
so that the module would not be twisted or bent by the fixture.
The fixing condition is shown as below:
At Room Temperature
LCD Module
Side Mount Fixing Screw
Gap=2mm
Bracket
Side Mount Fixing Screw
Stage
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Doc No.:
Issued Date: Mar. 27, 2008
Model No.: N133IB - L01
Tentative
5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin Symbol
Description
1 VSS Ground
2 VDD Power Supply +3.3 V
3 VDD Power Supply +3.3 V
4
VEDID
DDC +3.3 V
5 TEST Panel Self Test
6 CLKEDID DDC Clock
7 DataEDID DDC Data
8 Rxin0- LVDS Differential Data Input
9 Rxin0+ LVDS Differential Data Input
10 VSS Ground
11 Rxin1- LVDS Differential Data Input
12 Rxin1+ LVDS Differential Data Input
13 VSS Ground
14 Rxin2- LVDS Differential Data Input
15 Rxin2+ LVDS Differential Data Input
16 VSS Ground
17 CLK- LVDS Clock Data Input
18 CLK+ LVDS Clock Data Input
19 VSS Ground
20 VSS Ground
Note (1) Connector Part No.: DF19KR-20P-1H or equivalent
Note (2) User’s connector Part No: DF19G-20S-1C or equivalent
Note (3) The first pixel is odd as shown in the following figure.
Polarity
Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
-
-
Remark
-
-
-
R0~R5,G0-
G1~G5,B0,B1
-
B2~B5,Hsync,Vsync,DE
LVDS Level
-
-
5.2CTLIMK+ING DIAGRAM OF LVDS INPUT SIGNAL
Rxin2
T/7
IN20
IN19
IN18
IN17
IN16
Rxin1
DE
IN13
Vsync
IN12
Hsync
IN11
B5
IN10
B4
IN9
B1 B0 G5 G4 G3
Rxin0
IN5 IN4 IN3 IN2
G0 R5 R4 R3 R2
Signal for 1 DCLK Cycle (T)
IN15
B3
IN8
G2
IN1
R1
IN14
B2
IN7
G1
IN0
R0
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