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PDF M236H1-P07 Data sheet ( Hoja de datos )
| Número de pieza | M236H1-P07 | |
| Descripción | TFT LCD Module | |
| Fabricantes | CHI MEI | |
| Logotipo |  |
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Global LCD Panel Exchange Center
www.panelook.com
Issued Date: Sep. 21, 2009
Model No.: M236H1-P07
Approval
TFT LCD Approval Specification
MODEL NO.: M236H1-P07
Customer :
Approved by :
Note :
TPV
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2009-10-01
10:18:16
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2009.10.01
Director Accept
1 / 23
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1 page  
Global LCD Panel Exchange Center
www.panelook.com
Issued Date: Sep. 21, 2009
Model No.: M236H1-P07
Approval
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT (BASED ON CMO MODULE M236H1-L07)
Item
Storage Temperature
Operating Ambient Temperature
Symbol
TST
TOP
Value
Min. Max.
-20 +60
0 +50
Unit Note
ºC (1)
ºC (1), (2)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC)
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC)
(c) No condensation.
Note (2) The temperature of panel display surface area should be 0 ºC Min. and 60 ºC Max.
2.2 ABSOLUTE RATINGS OF ENVIRONMENT (OPEN CELL)
High temperature or humidity may reduce the performance of panel. Please store LCD panel within the
specified storage conditions.
Storage Condition: With packing
Storage temperature range: 25±5 ºC
Storage humidity range: 50±10%RH
Shelf life: 30days
2.3 ELECTRICAL ABSOLUTE RATINGS (OPEN CELL)
Item
Symbol
Value
Min
Power Supply Voltage
VCC -0.3
Logic Input Voltage
Vlogic
-0.3
Max
+6.0
+3.6
Unit
V
Note
(1)
Note (1) Permanent damage might occur if the module is operated at conditions exceeding the maximum
values.
5 / 23
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Issued Date: Sep. 21, 2009
Model No.: M236H1-P07
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
LVDS Clock
LVDS Data
Vertical Active Display Term
Horizontal Active Display
Term
Item
Frequency
Period
Input cycle to
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation
frequency
High Time
Low Time
Setup Time
Hold Time
Frame Rate
Total
Display
Blank
Total
Display
Blank
Symbol Min.
Fc 58.54
Tc -
Typ.
74.25
13.47
Max.
98
-
Unit
MHz
ns
Trcl -0.02*Tc - 0.02*Tc ns
Note
-
(1)
Fclkin_mod 0.98*Fc - 1.02*Fc MHz
FSSM
-
- 200 KHz
(2)
Tch - 4/7 - Tc
-
Tcl - 3/7 - Tc
-
Tlvs 600
Tlvh 600
-
-
- ps
- ps
(3)
Fr 50 60 75 Hz Tv=Tvd+Tvb
Tv 1115 1125 1136 Th
-
Tvd 1080 1080 1080 Th
-
Tvb 35 45 56 Th
-
Th 1050 1100 1150 Tc Th=Thd+Thb
Thd 960 960 960 Tc
-
Thb 90 140 190 Tc
-
Note: (1) Because this module is operated by DE only mode, Hsync and Vsync input signals should be
set to low logic level or ground. Otherwise, this module would operate abnormally.
INPUT SIGNAL TIMING DIAGRAM
DE
DCLK
DE
DATA
TVd
TC Thb
Tv
TVb
Th
Thd
11 / 23
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| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet M236H1-P07.PDF ] | |
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