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PDF L6565 Data sheet ( Hoja de datos )
| Número de pieza | L6565 | |
| Descripción | QUASI-RESONANT SMPS CONTROLLER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de L6565 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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L6565
QUASI-RESONANT SMPS CONTROLLER
s QUASI-RESONANT (QR) ZERO-VOLTAGE-
SWITCHING (ZVS) TOPOLOGY
s LINE FEED FORWARD TO DELIVER
CONSTANT POWER vs. MAINS CHANGE
s FREQUENCY FOLDBACK FOR OPTIMUM
STANDBY EFFICIENCY
s PULSE-BY-PULSE & HICCUP-MODE OCP
s ULTRA-LOW START-UP (< 70µA) AND
QUIESCENT CURRENT (< 3.5mA)
s DISABLE FUNCTION (ON/OFF CONTROL)
s 1% PRECISION (@ Tj = 25°C) INTERNAL
REFERENCE VOLTAGE
s ±400mA TOTEM POLE GATE DRIVER WITH
UVLO PULL-DOWN
s BLUE ANGEL, ENERGY STAR, ENERGY
2000 COMPLIANT
APPLICATIONS
s TV/MONITOR SMPS
s AC-DC ADAPTERS/CHARGERS
s DIGITAL CONSUMER
s PRINTERS, FAX MACHINES,
PHOTOCOPIERS AND SCANNERS
BLOCK DIAGRAM
1
INV
2.5V
COMP
2
-
+
VOLTAGE
REGULATOR
DIP8(Minidip)
SO-8
ORDERING NUMBERS:
L6565N
L6565D
DESCRIPTION
The L6565 is a current-mode primary controller IC,
specifically designed to build offline Quasi-resonant
ZVS (Zero Voltage Switching at switch turn-on) fly-
back converters.
Quasi-resonant operation is achieved by means of a
transformer demagnetization sensing input that trig-
gers MOSFET's turn-on.
VFF
3
LINE VOLTAGE
FEEDFORWARD
2V
-+
-+
40K 4
5pF
CS
January 2003
VCC
8
20V
INTERNAL
SUPPLY
R1
RQ
SQ
+ UVLO
R2
VREF2
-
ZERO CURRENT
DETECTOR
Blanking
START
+
2.1V
BLANKING
1.6V
-
Hiccup-mode
OCP
DRIVER
Starter
STOP
STARTER
VCC
7
GD
Hiccup-mode
OCP
5
ZCD
DISABLE
6
GND
1/17
1 page  
L6565
Figure 1. Supply current vs. Supply voltage
ICC
(mA)
10
5
1
0.5
0.1
0.05
0.01
0.005
0
0
CL = 1nF
f = 70KHz
TA = 25°C
5 10 15 20 VCC(V)
Figure 2. Start-up & UVLO vs. Temperature
14
VCC-ON
(V)
13
12
11
10
VCC-OFF
(V)
9
-25 0 25 50 75 100 125
T (°C)
Figure 3. Feedback reference vs. Temperature
VREF
(V)
D94IN048A
2.50
Figure 4. Line feedforward characteristics
Vcsx [V]
1.5
Upper clamp
5.0 V
1
4.5 V
4.0 V
0.5
3.5 V
3.0 V
VCOMP = 2.5V
0
0 0.5 1 1.5 2 2.5 3 3.5
VVFF [V]
Figure 5. Pin 2 (COMP) V-I characteristics
VCOMP [V]
6
5
Tj = 25 °C
Vpin1 = 0
4
3
2
Regulation
range
1
0
0 1234
ICOMP [mA]
Figure 6. ZCD blanking time vs. COMP voltage
TBLANK [µs]
20
Tj = 25 °C
15
10
2.48 5
2.46
-50 0 50 100 T (°C)
0
23456
VCOMP [V]
5/17
5 Page 
L6565
Error Amplifier Block (see fig. 17b):
The Error Amplifier (E/A) inverting input is used in primary feedback technique to compare a partition of the volt-
age generated by the auxiliary winding with the internal reference, to achieve converter's output voltage regu-
lation (see "Application Ideas", fig. 24). With secondary feedback (typically using a TL431 at the secondary side
and an optocoupler to transfer output voltage information to the primary side through the isolation barrier) the
E/A can be used as an inverting level-shifter to achieve negative feedback and shape the loop gain (see "Ap-
plication Ideas", fig. 23).
The E/A output is used typically for control loop compensation, realized with an RC network connected to the
inverting input. With other secondary feedback techniques, the output is driven directly by an emitter-grounded
optocoupler to modulate the duty cycle (the inverting input will be grounded in that case - see figure 23 in "Ap-
plication Ideas").
Current Comparator, PWM Latch and Hiccup-mode OCP (see fig. 17b):
The current comparator senses the voltage across the current sense resistor (Rs) and, by comparing it with the
programming signal delivered by the feedforward block, determines the exact time when the external MOSFET
is to be switched off. The PWM latch avoids spurious switching of the MOSFET, which might result from the
noise generated ("double-pulse suppression").
A comparator senses the voltage on the current sense input and disables the gate driver if the voltage at the pin
exceeds 2 V. Such anomalous condition is typically generated by a short circuit on the secondary rectifier or on
the secondary winding. To re-enable the driver, first the IC must be turned off and then can be restarted, that is
the Vcc voltage must fall below the UVLO threshold.
When the gate driver is disabled the quiescent current of the IC is unchanged and, since no energy is coming
from the self-supply circuit, the Vcc capacitor will be discharged below the UVLO threshold after some time.
Then the device will initiate a new start-up cycle. In case of failure of the secondary diode the resulting behavior
will be a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit.
Gate Driver (see fig. 18):
A totem pole buffer, with 400mA source and sink capability, drives the external MOSFET. It is made up of a
high-side NPN Darlington and a low-side MOSFET. In this way there is no need of an external diode clamp to
prevent the voltage at the gate drive output (pin 7, GD) from being pulled too negative.
An internal pull-down circuit holds the output low when the device is in UVLO conditions, to ensure that the ex-
ternal MOSFET cannot be turned on accidentally (e.g. at power-on).
Figure 18. Gate driver with UVLO pull-down
Vcc
8
DRIVER
L6565
7 GD
Q
UVLO
6
GND
11/17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet L6565.PDF ] | |
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