GP2010 Datasheet PDF - Mitel Networks Corporation
| Part Number | GP2010 | |
| Description | GPS Receiver RF Front End | |
| Manufacturers | Mitel Networks Corporation | |
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GP2010
GPS Receiver RF Front End
Supersedes edition in August 1996 Global Positioning Products Handbook, HB4305-1.0
DS4056 - 3.4 October 1996
The GP2010 is Mitel Semiconductor second generation
RF Front-end for Global Positioning System (GPS) receivers.
The GP2010 uses many innovative design techniques and a
leading-edge bipolar process to offer a low power, low cost
and high reliability RF Front End solution . The GP2010 is
designed to operate from either 3 or 5 Volt power supplies.
The input to the device is the L1 (1575.42MHz) Coarse-
Acquisition (C/A) code Global Positioning signal from an
antenna (via a low-noise pre-amplifier). The output is 2-bit
quantised for subsequent signal processing in the digital
domain. The GP2010 contains an on-chip synthesiser, mixers,
AGC and a quantiser which provides Sign and Magnitude
digital outputs. A minimum of external components is required
to make a complete GPS front-end.
The device has been designed to operate with the GP2021
12-channel Global Positioning Correlator, and DW9255 SAW
filter, both also available from Mitel Semiconductor.
FEATURES
s Low Voltage Operation (3V - 5V)
s Low Power - 200mW typ. (3V supply)
s C/A Code Compatible
s On-chip PLL Including Complete VCO
s Triple Conversion Receiver
s 44-Lead Surface Mount Quad Flat-Pack Package
s Sign and Magnitude Digital Outputs
s Compatible with GP2021 CMOS Correlator
APPLICATIONS
s C/A Code Global Positioning by Satellite Receivers
s Time Standards
s Navigation
s Surveying
ORDERING INFORMATION
The GP2010 is available in 44 pin Quad Flat pack (gullwing
formed leads) to Industrial (-40°C to +85°C) grade.
ORDERING CODE
GP2010 IG GPBR Industrial - Plastic 44-pin PQFP
34 22
35 21
36 20
37 19
38
39
GP2010
18
17
40 16
41 15
42 14
43 13
44 12
GP44
Pin Name
1 IF Output
2 PLL Filter 1
3 PLL Filter 2
4 VEE (OSC)
5 VCC (OSC)
6 VEE (OSC)
7 VEE (REG)
8 PRef
9 PReset
10 VEE (IO)
11 CLK
12 MAG
13 SIGN
14 OPCIK-
15 OPCIK+
16 VDD (IO)
17 PDN
18 TEST
19 LD
20 VEE (DIG)
21 AGC -
22 AGC +
Pin Name
23 VCC (DIG)
24 REF 2
25 REF 1
26 VCC (RF)
27 VEE (RF)
28 VEE (RF)
29 RF Input
30 VEE (RF)
31 VEE (RF)
32 VCC (RF)
33 O/P 1-
34 O/P 1+
35 VCC (2)
36 I/P 2-
37 I/P 2+
38 VEE (IF)
39 VEE (IF)
40 O/P 2-
41 O/P 2+
42 VCC (3)
43 I/P 3-
44 I/P 3+
Fig. 1 Pin connections - top view
RELATED PRODUCTS AND PUBLICATIONS
Part
Description
Data
Reference
DW9255
GP2021
GPSBuilder-2
GP2010
GP2015
GP2015
35.42MHz SAW Filter
Twelve-Channel Correlator
Twelve-Channel GPS receiver
development system
Design with the GP2010
Small RF Format Front End
Design with the GP2015
DS3861
DS4057
DS4004
AN4364
DS4374
AN4533
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GP2010
Characteristic
Value
Units
Min. Typ. Max.
Conditions
VCO Maximum Lock Frequency
VCO Minimum Lock Frequency
VCO regulator output voltage
VCO Gain
Phase Detector Gain
10MHz Reference Input
10MHz Reference Input Impedance
PLL Lockup Time
PLL Loop Gain
DIGITAL INTERFACES
Sample Clock, Power Down,
Test Inputs.
VIH
VIL
Input Current High IIH
Input Current Low IIL
Sign/Mag Outputs
VOH
VOL
Sample Clock to Sign/Mag Delay
40MHz Clock Output
High Level (VOH)
Low Level (VOL)
Output (differential)
Duty Cycle
LD (PLL Lock)/PReset Outputs
Low Level (VOL)
High Level (VOH)
Power-on Reset comparator input
Power Reset Reference Level
Power Reset Reference Input Current
1414
3
50
0.1
MHz
1386 MHz
3.3 3.5
V (Note 4)
150 240 MHz/V
5.3 V/rad (Note 7)
0.6 1.2 V pk-pk Pin 24
5 kΩ (Note 11)
6 ms From Power up (Note 7)
150 dB (Note 7)
Pins 11, 17, 18
2
0
-300
VDD
V
0.5 V
10 µA VIH = VDD
µA VIL = VEE
VDD-1
0.5
20
Pins 13, 12
V IO = -0.5mA
V IO = 0.5mA
ns CL = 15pF, RL = 15kΩ (Note 7)
VDD-1.25 VDD-1 VDD-0.8 V
VOH-0.1
V
220 mV p-p
43 %
Pins 14 & 15
(Note 5)
CL = 15pF (GND) (Note 7)
CL = 5pF (Diff) (Note 7)
(Note 7)
0.2 0.5
VDD-1 VDD
Pins 19 and 9
V IO = 0.5mA
V IO = -10µA
Pin 8
1.1 1.35 V
-10 10 µA
Notes On Electrical Characteristics:- All RF measurements are made with appropriate matching to the input or output
impedances, such as balun transformers, and levels refer to matched 50ohm ports (see figure 3 for test circuit)
1. RF input impedance (series) without input matching components connected - expressed as Real impedance with reactive
inductor value. Measured at 1575.42MHz.
2. Input matched to 50ohm, output loaded wlth 600ohms differential
3. Maximum Stage 3 input signal amplitude for correct AGC operation = 20mV rms.
4. VCO regulator voltage measured with respect to Vcc (OSC) - pin 5.
5. OPCLK outputs are differential and are referenced to VDD.
6. Minimum gain requirement expressions:
-7dBm < -174dBm/Hz + 19dB + G1 + G2 + G3 - 21dB + 63dB
where -7dBm = typical IF Output level with AGC active (equivalent to 100mV rms)
-174dBm/Hz = background noise level at RF input
19dB = sum of LNA gain and noise figure
-21dB = total loss in 175MHz and 35MHz filters
63dB = summation of noise over a 2MHz bandwidth
Rearranging the above expression gives G1 + G2 + G3 > 106dB.
7. This parameter is not production tested.
8. This impedance is toleranced at +/-30% and is not production tested.
9. Roll off occurs in on-chip capacitive coupling IF Output to input of ADC circuit. Not measurable at IF Output.
10. CW input on pins 43 & 44 of 35.42MHz at 7mV rms.
11. This input impedance applies to the typical input level. The impedance is level dependent and is not tested or guaranteed.
5
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| Information | Total 24 Pages | |
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| Download | [ GP2010.PDF Datasheet ] | |
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