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PDF LIS-1024D-LG Data sheet ( Hoja de datos )
| Número de pieza | LIS-1024D-LG | |
| Descripción | High Performance Linear CMOS Image Sensor | |
| Fabricantes | Panavision Imaging | |
| Logotipo |  |
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ONE TE C H N O L O G Y PLACE – HOMER, NEW YORK 13077
TEL: +1 607 749 2000 FAX: +1 607 749 3295 www.PanavisionImaging.com / [email protected]
LIS-1024
High Performance Linear CMOS Image Sensor
The LIS-1024 image sensor is a high performance, very low noise linear image sensor designed for a wide variety
of applications including:
P/N: LIS-1024D-LG
16-pin LCC package
• Spectroscopy
• Bar Code Reading
• Edge Detection
• Contact Scanning
• Optical Character Recognition
• Encoding
• Position Detection
• And more.......
Description
The LIS-1024 Image Sensor consist of an array of ultra low dark current photo-diode pixels with performance
exceeding most Charge-Coupled Devices (CCD's). The device has multiple read out modes, including: Non-
Destructive, Dynamic Pixel Reset™ (DPR), and Frame Reset.
The Non-destructive mode enables extremely low noise measurements (approaching a single electron) through the
use of signal averaging, enabling the system to achieve near single electron noise performance, making the device
ideally suited for any high performance measurement application. In DPR mode, each pixel is reset as it is read,
ensuring each pixel integrates for the same amount of time. Other reset modes are also provided to give
exceptional control over exposure time and pixel read out. The Sensor also operates over an extended power
supply range of 2.8-5.0 VDC.
Operation is simplified by on-chip logic. The only external signals required are a clock with a frequency equal to
the desired pixel read rate, a reset mode selection, and an external reset to initiate read-out when running
asynchronously.
The LIS-1024 is supplied in a 16-pin LCC package as shown above.
PDS0001 REV R 04/14/09
© Panavision Imaging LLC 2004 -2009 All rights reserved.
Subject to change without notice.
Page 1 of 13
1 page  
RST pin is used for external reset. RST may be initiated asynchronously One full frame of video may be required
to achieve valid data, dependant on when RST is initiated in DPR modes. Active high, RST resets the internal
counter, and resets pixels when PRE is held low. Initiating RST pin interrupts SYN output.
NOTES TO TIMING DIAGRAMS
1. Clock duty cycle should be 40% to 60%.
2. 1024 Clock cycles for the number of pixels to read, starting at the first pixel.
3. t int represents integration time.
4. t cnt represents clock cycle count
5. t rpix represents time between falling edge of RST and 1st rising edge of CLKIN
6. RST pulse always resets internal counter, thus next pixel output is the first pixel.
Figure 1: LIS-1024 Free Running Timing Setup
t cnt: 1023 1024 1025 1026
CLK
1027
1028
1029
1
2
SYN
PRE & RMS
Recommended
t sdly
Mode Setup
Internal Reset
VO
Pixel
1023
Pixel
1024
t
pcdly
Pixel 1
Pixel 2
t spix
Integration Begins
Figure 2: LIS-1024 External Reset Timing Setup (PRE Held High)
t cnt: N N +1 N +2 N +3 N +4 N +5 N +6
1
2
CLK
RST
VO
Asynchronous Reset
Pixel N Pixel N +1 Pixel N +2
1st Pixel Read out
on next Rising Edge
t pcdly
Pixel 1
Pixel 2
Integration Begins
Figure 3: LIS-1024 External Reset Timing Setup Using PRE To Control Pixel Reset & Integration
t cnt:
N
N +1 N +2 N +3 N +4 N +5 N +6
1
2
CLK
PRE
Asynchronous Reset
Pixels in Reset
Integration Begins
RST
1st Pixel Read out
on next Rising Edge
t pcdly
VO Pixel N
Pixel 1
Pixel 2
PDS0001 REV R 04/14/09
© Panavision Imaging LLC 2004 -2009 All rights reserved.
Subject to change without notice.
Page 5 of 13
5 Page 
TYPICAL APPICATION CIRCUIT:
The following shows the LIS-1024 in a common application, interfacing to a A/D converter.
VDD
+
10uf .01uf
VDD
SYNCOUT SYN
CLOCK
ASIC/FPGA PIXRSTENA
RESET MODE
CLK
LIS-1024
PRE
VO
RMS
LOW PASS FILTER
IN OUT
GND
TOA/D
RESET RST DESIGNLOWPASSFILTERFOR1/2CLOCKRATE
GND
PDS0001 REV R 04/14/09
© Panavision Imaging LLC 2004 -2009 All rights reserved.
Subject to change without notice.
Page 11 of 13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet LIS-1024D-LG.PDF ] | |
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