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PDF CCD525 Data sheet ( Hoja de datos )
| Número de pieza | CCD525 | |
| Descripción | Time Delay Integration Line Scan Sensor | |
| Fabricantes | Fairchild Imaging | |
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Hay una vista previa y un enlace de descarga de CCD525 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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CCD525
Time Delay Integration
Line Scan Sensor
FEATURES
2048 Active Pixels Per Line
96 TDI Lines
13µm x13 µm Pixels
4 High Speed Output Ports
TDI Stages Selectable Between 96, 64, 48,
32, or 24
100 MHz Data Rate with 4 Outputs
Operating at 25 MHz
42 kHz Line Rate
2000X Antiblooming Protection
High Sensitivity
RoHS Compliant
GENERAL DESCRIPTION
The CCD525 is a Time Delay Integration (TDI)
sensor designed for a wide range of imaging
applications requiring high speed operation
combined with high sensitivity. The sensor is
capable of producing a total data rate of 100 MHz
(line rate > 42 kHz). The CCD has a total imaging
area of 2048 contiguous elements by 96 TDI rows.
The pixel dimensions are 13µm by 13µm. The
CCD overall dimensions are 27.940 mm x 3.302
mm. The sensor is mounted in a custom 40-pin
dual-in-line ceramic package.
The CCD525 imaging area is controlled by 3-
phase timing, and exposure control is performed
by selecting the number of active TDI stages.
Independent TDI control gates allow the following
number of TDI stages to be selected: 96, 64, 48,
32, or 24. The CCD525 features lateral anti-
blooming structures capable of 2000X over-
saturation protection.
The vertical (parallel) imaging register is
separated from the horizontal (serial) registers by
50 isolation rows. The isolation rows are also
controlled by 3-phase timing. The isolation rows
are covered with a light shield and are used to
transfer the charge from the imaging area to four
horizontal registers. The horizontal registers are
controlled by 4-phase timing. The design of the
horizontal registers has been optimized for high
charge transfer efficiency at low signal levels.
Each horizontal register is connected to a high
speed output amplifier. The output amplifier is a
three-stage source follower designed for high
conversion gain and extended bandwidth.
DEVICE ARCHITECTURE
The CCD525 operates in buried channel mode for
optimal performance. The imaging area consists
of 2048 contiguous pixels by 96 rows.
Photogenerated charge is integrated in this
region, then following the integration time, the
charge is transferred line by line to the adjacent
isolation rows for readout. The number of active
TDI rows is simply controlled by biasing the
appropriate control gates, VSWxx, low. Normal
vertical timing is employed across the array
irrespective of the selected number of active TDI
stages. The last gate in the vertical register is also
called the vertical transfer gate, ΦX. The charge is
transferred from the vertical register to the
horizontal registers when ΦX is clocked low. The
horizontal registers require 4-phase timing.
Charge is transferred, pixel by pixel, to the floating
diffusion sense node where it produces a voltage
change corresponding to the signal level. After the
signal is sampled, the reset gate is clocked high
to clear the signal, and restore the potential of the
sense node to the VRD reset drain voltage. There
are 3 prescan elements in each video line.
Fairchild Imaging • 1801 McCarthy Blvd. • Milpitas CA 95035 USA • (800) 325-6975 • Rev A • Page 1 of 6
1 page  
CCD CLOCK TIMING
CCD525 Vertical Clock Timing
CCD525 Horizontal Clock Timing
Fairchild Imaging • 1801 McCarthy Blvd. • Milpitas CA 95035 USA • (800) 325-6975 • Rev A • Page 5 of 6
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CCD525.PDF ] | |
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