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PDF CCD5061 Data sheet ( Hoja de datos )
| Número de pieza | CCD5061 | |
| Descripción | 6k x 128 Element Time Delay Integration Sensor | |
| Fabricantes | Fairchild Imaging | |
| Logotipo |  |
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Fairchild Imaging CCD 5061
6k x 128 Element, Time Delay Integration Sensor
PRODUCT DESCRIPTION
The CCD5061 is a 6144 pixel x 128 line, high speed
TDI sensor. The active imaging area is organized as
6144 vertical columns and 128 horizontal TDI rows.
The array is set up for bi-directional operation. There
are identical output registers and amplifiers on both
the top and the bottom of the array. The outputs to be
used (either top or bottom) are user-selectable and
controlled by the vertical clock timing. In addition, the
exposure level can be controlled by reducing the
number of TDI rows from 128 to 96, 64, 32, 16, 8 or 4.
This is also user-selectable and is accomplished by
supplying the appropriate phasing for the vertical
clocks within each section. For instance, if 64 lines of
TDI were required, the vertical clocks for lines 65-128
would be connected to a high potential, which would
drain these unused rows out to the opposite side
(unused) of the array to be dumped into the VOFD
drain. With four outputs, each running at 20MHz, the
CCD5061 can provide a total data rate of 80MHz
enabling the CCD to run at better than 12kHz line rate.
Utilizing Fairchild Imaging proprietary buried channel
CCD process, the CCD5061 achieves consistent,
superior TDI performance.
The active imaging area is separated from the four
horizontal output registers by 21 isolation rows. These
isolation rows are covered by a metal lightshield to
protect them while charge transfers to the output
registers. Both the active imaging area and the
isolation region utilize 3-phase clocking.
The four horizontal output registers utilize 4-phase
clocking. Special design techniques have been
implemented to maximize charge transfer efficiency
especially at low light levels. The output amplifier is a
3-stage source follower configuration. This allows
maximum scale factor (charge to voltage conversion)
and maximum bandwidth.
The CCD5061 is housed in a custom 176 pin (100 mil
grid) ceramic PGA package. It has an AR coated
window.
FEATURES
6144 pixels per line
Number of TDI stages electronically selectable; 4, 8, 16, 32, 64, 96, 128
Bi-directional TDI (shift up or down)
4 outputs – each capable of 20MHz data rate – 80 MHz total data rate per side (shift up or
down)
100% fill factor
8.75µm x 8.75 µm pixel size
On-chip binning capability
IMAGING SOLUTIONS
1 page  
Block Diagram of Sector “x” (where x={1, 2, …8} for CCD10121, x={1, 2, ...6} for CCD8091, x={1, 2, …4} for CCD5061.)
VTG-T
V1HS-T, V2HS-T, V3HS-T
H1-Tx, H2-Tx, H3-Tx, H4-Tx
3 top opaqued taper (fast) readout rows
FOG-Tx, VOG-Tx
VRD-Tx
RG-Tx
VOUT-Tx
V1X-T, V2X-T, V3X-T
VSW128-D
V1A-T, V2A-T, V3A-T
VSW4-U
V1C-T, V2C-T, V3C-T
VSW8-U
V1D-T, V2D-T, V3D-T
VSW16-U
18 top opaqued taper (slow) readout rows
Top pixel rows 1~4
Top pixel rows 5~8
Top pixel rows 9~16
18+3 = 21 total
opaqued taper rows
V1E-T, V2E-T, V3E-T
Top pixel rows 17~32
VSW32-U
V1F-T, V2F-T, V3F-T
VSW64
V1F-B, V2F-B, V3F-B
Top pixel rows 33~64
Bottom pixel rows 33~64
128 TDI pixel rows
@ 8.75m/row
= 1.12mm
VSW32-D
V1E-B, V2E-B, V3E-B
VSW16-D
V1D-B, V2D-B, V3D-B
VSW8-D
V1C-B, V2C-B, V3C-B
VSW4-D
V1A-B, V2A-B, V3A-B
VSW128-U
V1X-B, V2X-B, V3X-B
V1HS-B, V2HS-B, V3HS-B
VTG-B
Bottom pixel rows 17~32
Bottom pixel rows 9~16
Bottom pixel rows 5~9
Bottom pixel rows 1~4
18 bottom opaqued taper (slow) readout rows
18+3 = 21 total
opaqued taper rows
3 bottom opaqued taper (fast) readout rows
H1-Bx, H2-Bx, H3-Bx, H4-Bx
FOG-Bx, VOG-Bx
1536 pixel columns/sector @ 8.75m/column = 13.44mm
VOUT-Bx
RG-Bx
VRD-Bx
5 Page 
Output Amplifier Voltages & External Load Resistor
Symbol
Parameter
Min Typ Max Unit
Remarks
VDD
VRD
VOFD
VSRC
VGT
VOG
VSS
RLOAD
Amplifier DC Supply
Reset Drain
Overflow Drain
Current source (“signal ground”)
from amplifier 1st & 2nd stages
Bias voltage for amplifier 1st & 2nd-
stage constant-current-source FETs
Output Gate DC Bias
Substrate [Ground]
Output Load on each VOUT pin to
VSS
+23
+16
+16
+2.5
+4
-4
0
0.9 1.0
V IDD+15mA /pin. See note 1
V See note 1
V See note 2
V ISRC -1.5mA /pin
V IGT < 1nA /pin
V IOG < 1nA /pin
V
k If the external preamp has
<100kequivalent input
resistance, then increase RLOAD so
that the total equivalent resistance
from VOUT to VSS is 1.0k
Note 1: Whenever VDD>+12V, VRD must be biased at not less than 12V less than VDD:
VRD(VDD-12V), for all VDD>+12V
A zener diode circuit is recommended to ensure that this condition is always met. If this condition
is not met, even momentarily, then permanent damage to the output amplifier(s) may result.
Note 2: (VRD-2V)<VOFD<(VRD+2V) If this condition is not met, even momentarily (for example, during
power-up or power-down), then permanent damage to the CCD gates may result.
Absolute Maximum Ratings
Pin Names (suffixes not listed below)
VSS
VDD, VRD, VOFD, VOUT, VSRC, VGT
All other pins
Voltage between adjacent CCD gates
Storage temperature
Operating temperature
Min Max Unit
Remarks
0 0 V Must be grounded to 0V when device is being
handled. Do not “float”.
-0.4 +25 V Each pin has a diode to VSS on the chip
-5 +20 V
-24 +24 V Block diagram shows adjacent gates.
-40 +70 C
-40 +60 C
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet CCD5061.PDF ] | |
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