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Numéro de référence | CCD10121 | ||
Description | 12K x 128 Element Delay and Integration CCD | ||
Fabricant | Fairchild Imaging | ||
Logo | |||
CCD 10121
12K x 128 Element
TDI – Time, Delay and Integration CCD
FEATURES
• 12,288 pixels per line
• Number of TDI stages electronically
selectable: {4, 8, 16, 32, 64, 96, 128}
• Bi-directional TDI (shift up or down)
• 8 outputs — each capable of 20MHz data
rate — 160MHz total data rate
• 100% fill factor
• 8.75µm x 8.75µm pixel size
• On-chip binning capability
GENERAL DESCRIPTION
The CCD 10121 is a 12,288 pixel x 128 line,
high speed TDI sensor. The active imaging
area is organized as 12,288 vertical columns
and 128 horizontal TDI rows. The array is set
up for bi-directional operation. There are
identical output registers and amplifiers on both
the top and the bottom of the array. The
outputs to be used (either top or bottom) are
user-selectable and controlled by the vertical
clock timing. In addition, the exposure level
can be controlled by reducing the number of
TDI rows from 128 to 96, 64, 32, 16, 8 or 4.
This is also user-selectable and is
accomplished by supplying the appropriate
phasing for the vertical clocks within each
section. For instance, if 64 lines of TDI were
required, the vertical clocks for lines 65-128
would be connected to a high potential, which
would drain these unused rows out to the
opposite side (unused) of the array to be
dumped into the VOFD drain. With eight
outputs, each running at 20MHz, the CCD
10121 can provide a total data rate of 160MHz
enabling the CCD to run at better than 12kHz
line rate. Utilizing Fairchild Imaging proprietary
buried channel CCD process, the CCD 10121
achieves consistent, superior TDI performance.
The active imaging area is separated from the
eight horizontal output registers by 21 isolation
rows. These isolation rows are covered by a
metal lightshield to protect them while charge
transfers to the output registers. Both the
active imaging area and the isolation region
utilize 3-phase clocking.
The eight horizontal output registers utilize
4-phase clocking. Special design techniques
have been implemented to maximize charge
transfer efficiency especially at low light
levels. The output amplifier is a 3-stage
source follower configuration. This allows
maximum scale factor (charge to voltage
conversion) and maximum bandwidth.
The CCD 10121 is housed in a custom 480
pin (100 mil grid) ceramic PGA package. It
has an AR coated window.
FUNCTIONAL DESCRIPTION
The following functional elements are
illustrated in the block diagram:
Image Sensing Elements: These are
elements of a line of 12,288 image sensors
separated by channel stops and covered by
a passivation layer. Incident photons pass
through a transparent polycrystalline silicon
gate structure creating electron hole pairs.
The resulting photoelectrons are collected in
the photosites during the integration period.
The amount of charge accumulated in each
photosite is a linear function of the localized
incident illumination intensity and integration
period.
Transfer Gates: This gate is a structure
adjacent to the row of image sensor
elements. The charge packets accumulated
in the photosites are transferred in parallel
via the transfer gate to the transport shift
1801 McCarthy Blvd.• Milpitas CA 95035 • (800) 325-6975 • Fax (408) 435-7352 • www.fairchildimaging.com • Rev NR • 1 of 5
This data sheet is acceptable for export.
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Pages | Pages 5 | ||
Télécharger | [ CCD10121 ] |
No | Description détaillée | Fabricant |
CCD10121 | 12K x 128 Element Delay and Integration CCD | Fairchild Imaging |
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