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PDF AD6674 Data sheet ( Hoja de datos )
| Número de pieza | AD6674 | |
| Descripción | 385 MHz BW IF Diversity Receiver | |
| Fabricantes | Analog Devices | |
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Data Sheet
385 MHz BW IF Diversity Receiver
AD6674
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
In band SFDR = 83 dBFS at 340 MHz (750 MSPS)
In band SNR = 66.7 dBFS at 340 MHz (750 MSPS)
1.4 W total power per channel at 750 MSPS (default settings)
Noise density = −153 dBFS/Hz at 750 MSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
Flexible input range
AD6674-750 and AD6674-1000
1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
AD6674-500
1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient automatic gain control
(AGC) implementation
Noise shaping requantizer (NSR) option for main receiver
function
Variable dynamic range (VDR) option for digital
predistortion (DPD) function
2 integrated wideband digital processors per channel
12-bit numerically controlled oscillator (NCO), up to
4 cascaded half-band filters
Differential clock inputs
Integer clock divide by 1, 2, 4, or 8
Energy saving power-down modes
Flexible JESD204B lane configurations
Small signal dither
APPLICATIONS
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
GENERAL DESCRIPTION
The AD6674 is a 385 MHz bandwidth mixed-signal
intermediate frequency (IF) receiver. It consists of two, 14-bit
1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters
(ADC) and various digital signal processing blocks consisting of
four wideband DDCs, an NSR, and VDR monitoring. It has an
on-chip buffer and a sample-and-hold circuit designed for low
power, small size, and ease of use. This product is designed to
support communications applications capable of sampling wide
bandwidth analog signals of up to 2 GHz. The AD6674 is
optimized for wide input bandwidth, high sampling rate,
excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
AVDD1
(1.25V)
FUNCTIONAL BLOCK DIAGRAM
AVDD2
(2.5V)
AVDD3 AVDD1_SR DVDD
(3.3V)
(1.25V)
(1.25V)
DRVDD
SPIVDD
(1.25V) (1.8V TO 3.3V)
VIN+A
VIN–A
BUFFER
FD_A
FD_B
VIN+B
VIN–B
BUFFER
ADC
SIGNAL
MONITOR
ADC
V_1P0
CLK+
CLK–
CLOCK
GENERATION
÷2
÷4
÷8
SIGNAL PROCESSING
DDDIDIGGIGIIGITTITIAATALALLLDDDODOOWOW(W(×WN(×N4(×N4×CN)4)C4O)C)CONOONVNNVEVVEREERSRRSISOSIOINOIONNN
NNOOISISEESSHHAAPPININ((×G×G22R)R)EEQQUUAANNTTIZIZEERR
VVAARRIAIABBLLEEDDYYNNAAMMICICRRAANNGGEE
((××22))
4
JESD204B
SUBCLASS 1
CONTROL
FAST
DETECT
SIGNAL
MONITOR
SPI CONTROL
AD6674
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
PDWN/
STBY
AGND
SYSREF± SYNCINB± SDIO SCLK CSB
Figure 1.
DGND DRGND
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD6674
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate, 1.0 V internal reference (VREF), AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Voltage
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage Range
(Internal VREF = 1.0 V)
Common-Mode Voltage (VCM)
Differential Input Capacitance1
Analog Full Power Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
AVDD1_SR
DVDD
DRVDD
SPIVDD
IAVDD12
IAVDD22
IAVDD32
IAVDD1_SR2
IDVDD2
IDRVDD2, 3
L = 2 Mode4
ISPIVDD
Temp
AD6674-1000
Min Typ Max
14
AD6674-750
Min Typ Max
AD6674-500
Min Typ Max
14
Unit
Bits
Full Guaranteed
Guaranteed
Guaranteed
Full −0.31 0
+0.31 −0.51 0
+0.42 −0.3 0
+0.3 % FSR
Full
0 +0.23
0 +0.41
0 +0.3 % FSR
Full −6
0
+6 −6 0 +6 −6 0 +6 % FSR
Full
1 +4.5
1 +5.2
1 +5.1 % FSR
Full −0.7 ±0.5 +0.8 −0.6 ±0.5 +0.8 −0.6 ±0.5 +0.7 LSB
Full −5.7 ±2.5 +6.9 −3.4 ±2.5 +5.0 −4.5 ±2.5 +5.0 LSB
Full −14
Full ±13.8
−9 −9 ppm/°C
−57 ±25 ppm/°C
Full 1.0
1.0 1.0 V
25°C 2.63
2.48 2.06 LSB rms
Full 1.46 1.70 1.94 1.46 1.70 1.94 1.46 2.06 2.06 V p-p
Full 2.05
Full 1.5
Full 2
2.05 2.05 V
1.5 1.5 pF
2 2 GHz
Full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 V
Full 2.44 2.50 2.56 2.44 2.50 2.56 2.44 2.50 2.56 V
Full 3.2 3.3 3.4 3.2 3.3 3.4 3.2 3.3 3.4 V
Full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 V
Full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 V
Full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 V
Full 1.8
3.3 1.8
3.3 1.8
3.3 V
Full
685 721
545 623
427 466 mA
Full
595 677
460 572
398 463 mA
Full
125 142
125 142
89 100 mA
Full 16 18
10 17
10 18 mA
Full
263 292
165 217
139 183 mA
Full
200 225
190 258
182 237 mA
25°C
N/A5
N/A5
140 mA
Full 5 6
5 7.0
5 7 mA
Rev. A | Page 5 of 90
5 Page 
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Electrical
AVDD1 to AGND
AVDD1_SR to AGND
AVDD2 to AGND
AVDD3 to AGND
DVDD to DGND
DRVDD to DRGND
SPIVDD to AGND
AGND to DRGND
VIN±x to AGND
SCLK, SDIO, CSB to AGND
PDWN/STBY to AGND
Operating Temperature Range
Junction Temperature Range
Storage Temperature Range
(Ambient)
Rating
1.32 V
1.32 V
2.75 V
3.63 V
1.32 V
1.32 V
3.63 V
−0.3 V to +0.3 V
3.2 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to SPIVDD + 0.3 V
−40°C to +85°C
−40°C to +115°C
−60°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
AD6674
THERMAL CHARACTERISTICS
Typical θJA, ΨJB, and θJC are specified vs. the number of printed
circuit board (PCB) layers in different airflow velocities (in
m/sec). Airflow increases heat dissipation, effectively reducing
θJA and ΨJB. In addition, metal in direct contact with the package
leads and exposed pad from metal traces, through holes, ground,
and power planes reduces the θJA. Thermal performance for
actual applications requires careful inspection of the conditions
in an application. The use of appropriate thermal management
techniques is recommended to ensure that the maximum
junction temperature does not exceed the limits shown in Table 6.
Table 7. Thermal Resistance Values
PCB
Type
Airflow
Velocity
(m/sec)
θJA
ΨJB
JEDEC
2s2p
Board
0.0
1.0
2.5
17.81, 2
15.61, 2
15.01, 2
6.31, 3
5.91, 3
5.71, 3
θJC_TOP
4.71, 5
N/A4
N/A4
θJC_BOT
1.21, 5
Unit
°C/W
°C/W
°C/W
1 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per JEDEC JESD51-8 (still air).
4 N/A means not applicable.
5 Per MIL-STD 883, Method 1012.1.
ESD CAUTION
Rev. A | Page 11 of 90
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD6674.PDF ] | |
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