PDF N25Q512A Data sheet ( Hoja de datos )

Número de pieza	N25Q512A
Descripción	NOR Flash Memory
Fabricantes	Micron
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No Preview Available ! 512Mb, Multiple I/O Serial Flash Memory Features Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A Features • Stacked device (two 256Mb die) • SPI-compatible serial bus interface • Double transfer rate (DTR) mode • 2.7–3.6V single supply voltage • 108 MHz (MAX) clock frequency supported for all protocols in single transfer rate (STR) mode • 54 MHz (MAX) clock frequency supported for all protocols in DTR mode • Dual/quad I/O instruction provides increased throughput up to 54 MB/s • Supported protocols – Extended SPI, dual I/O, and quad I/O – DTR mode supported on all • Execute-in-place (XIP) mode for all three protocols – Configurable via volatile or nonvolatile registers – Enables memory to work in XIP mode directly af- ter power-on • PROGRAM/ERASE SUSPEND operations • Available protocols – Available READ operations – Quad or dual output fast read – Quad or dual I/O fast read • Flexible to fit application – Configurable number of dummy cycles – Output buffer configurable • Software reset • Additional reset pin for selected part numbers 1 • 3-byte and 4-byte addressability mode supported • 64-byte, user-lockable, one-time programmable (OTP) dedicated area • Erase capability – Subsector erase 4KB uniform granularity blocks – Sector erase 64KB uniform granularity blocks – Single die erase • Write protection – Software write protection applicable to every 64KB sector via volatile lock bit – Hardware write protection: protected area size defined by five nonvolatile bits (BP0, BP1, BP2, BP3, and TB) – Additional smart protections, available upon re- quest • Electronic signature – JEDEC-standard 2-byte signature (BA20h) – Unique ID code (UID): 17 read-only bytes, including: Two additional extended device ID bytes to identify device factory options; and cus- tomized factory data (14 bytes) • Minimum 100,000 ERASE cycles per sector • More than 20 years data retention • Packages – JEDEC-standard, all RoHS-compliant – V-PDFN-8/8mm x 6mm (also known as SON, DFPN, MLP, MLF) – SOP2-16/300mils (also known as SO16W, SO16- Wide, SOIC-16) – T-PBGA-24b05/6mm x 8mm (also known as TBGA24) Note: 1. Part numbers: N25Q512A83G1240x, N25Q512A83GSF40x, N25Q512A83GSFA0x,N25Q512A83G12A0x and N25Q512A83G12H0x see table 43 for x last digit details PDF: 09005aef84752721 n25q_512mb_1ce_3V_65nm.pdf - Rev. T 08/14 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2011 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1 page 512Mb, Multiple I/O Serial Flash Memory Features List of Tables Table 1: Signal Descriptions ........................................................................................................................... 10 Table 2: Sectors[1023:0] ................................................................................................................................. 13 Table 3: Data Protection Using Device Protocols ............................................................................................. 14 Table 4: Memory Sector Protection Truth Table .............................................................................................. 14 Table 5: Protected Area Sizes – Upper Area ..................................................................................................... 14 Table 6: Protected Area Sizes – Lower Area ...................................................................................................... 15 Table 7: SPI Modes ........................................................................................................................................ 16 Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................ 18 Table 9: Status Register Bit Definitions ........................................................................................................... 20 Table 10: Nonvolatile Configuration Register Bit Definitions ........................................................................... 21 Table 11: Volatile Configuration Register Bit Definitions .................................................................................. 22 Table 12: Sequence of Bytes During Wrap ....................................................................................................... 23 Table 13: Supported Clock Frequencies – STR ................................................................................................. 23 Table 14: Supported Clock Frequencies – DTR ................................................................................................ 23 Table 15: Extended Address Register Bit Definitions ........................................................................................ 25 Table 16: Enhanced Volatile Configuration Register Bit Definitions .................................................................. 25 Table 17: Flag Status Register Bit Definitions .................................................................................................. 26 Table 18: Command Set ................................................................................................................................. 28 Table 19: Lock Register .................................................................................................................................. 36 Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands ....................................... 40 Table 21: Read ID Data Out ............................................................................................................................ 40 Table 22: Extended Device ID, First Byte ......................................................................................................... 40 Table 23: Extended Device ID, Second Byte .................................................................................................... 41 Table 24: Serial Flash Discovery Parameter Data Structure .............................................................................. 42 Table 25: Parameter ID .................................................................................................................................. 42 Table 26: Command/Address/Data Lines for READ MEMORY Commands ....................................................... 45 Table 27: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address ............................. 46 Table 28: Data/Address Lines for PROGRAM Commands ................................................................................ 56 Table 29: Suspend Parameters ....................................................................................................................... 68 Table 30: Operations Allowed/Disallowed During Device States ...................................................................... 69 Table 31: Reset Command Set ........................................................................................................................ 70 Table 32: OTP Control Byte (Byte 64) .............................................................................................................. 72 Table 33: XIP Confirmation Bit ....................................................................................................................... 75 Table 34: Effects of Running XIP in Different Protocols .................................................................................... 75 Table 35: Power-Up Timing and VWI Threshold ............................................................................................... 78 Table 36: AC RESET Conditions ...................................................................................................................... 79 Table 37: Absolute Ratings ............................................................................................................................. 83 Table 38: Operating Conditions ...................................................................................................................... 83 Table 39: Input/Output Capacitance .............................................................................................................. 83 Table 40: AC Timing Input/Output Conditions ............................................................................................... 84 Table 41: DC Current Characteristics and Operating Conditions ...................................................................... 85 Table 42: DC Voltage Characteristics and Operating Conditions ...................................................................... 85 Table 43: AC Characteristics and Operating Conditions ................................................................................... 86 Table 44: Part Number Information ................................................................................................................ 91 Table 45: Package Details ............................................................................................................................... 92 PDF: 09005aef84752721 n25q_512mb_1ce_3V_65nm.pdf - Rev. T 08/14 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2011 Micron Technology, Inc. All rights reserved. 5 Page 512Mb, Multiple I/O Serial Flash Memory Signal Descriptions Table 1: Signal Descriptions (Continued) Symbol HOLD# W# VPP VCC VSS DNU NC Type Control Input Control Input Power Power Ground – – Description HOLD: Pauses any serial communications with the device without deselecting the device. DQ1 (output) is High-Z. DQ0 (input) and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW. HOLD# is used for input/output during the following operations: QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an I/O (DQ3 functionality), and the HOLD# functionality is disabled when the device is selected. When the device is deselected (S# is HIGH) in parts with RESET# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR. On devices that include DTR mode capability, the HOLD# functionality is disabled as soon as a DTR operation is recognized. Write protect: W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If voltage range is low (0V to VCC), the signal acts as a write protection control input. The memory size protected against PROGRAM or ERASE opera- tions is locked as specified in the status register block protect bits 3:0. W# is used as an input/output (DQ2 functionality) during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations and in QIO-SPI. Supply voltage: If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the addition- al VPP power supply to speed up internal operations. However, to enable this functionality, it is necessary to set bit 3 of the VECR to 0. In this case, VPP is used as an I/O until the end of the operation. After the last input data is shif- ted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed. The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled. Device core power supply: Source voltage. Ground: Reference for the VCC supply voltage. Do not use. No connect. PDF: 09005aef84752721 n25q_512mb_1ce_3V_65nm.pdf - Rev. T 08/14 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2011 Micron Technology, Inc. All rights reserved. 11 Page

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