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PDF LTM12C324S Data sheet ( Hoja de datos )
| Número de pieza | LTM12C324S | |
| Descripción | TFT LCD Module | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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LIQUID CRYSTAL DISPLAY DIVISION
PRODUCT INFORMATION
FEATURES
(1) 12.1”XGA display size for notebook PC
(2) LVDS interface system
31cm COLOUR TFT-LCD MODULE
(12.1 TYPE)
LTM12C324S
(p-Si TFT)
TENTATIVE
MECHANICAL SPECIFICATIONS
Item
Dimensional Outline (typ.)
Number of Pixels
Active Area
Pixel Pitch
Weight (approximately)
Backlight
Specifications
261.0(W) x 197.5(H) x 4.9max(D) mm
1024(W) x 768(H) pixels
245.76(W) x 184.32(H) mm
0.24(W) x 0.24(H)
275g
Single CCFL, Sidelight type
ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage (VDD)
(VFL)
FL Driving Frequency (fFL)
Input Signal Voltage (VIN)
Operating Temperature
Storage Temperature
Storage Humidity
Min. Max. Unit
-0.3 4.0
V
0 2.0 kV(rms)
- 100 kHz
-0.3 VDD+0.3
V
0 50 °C
-20 60
°C
10 90 %(RH)
ELECTRICAL SPECIFICATION
Item Min. Typ. Max. Unit
Supply Voltage
(VDD)
3.0 3.3 3.6
V
(VFL)
530 580 630 V(rms)
FL Start Voltage (Ta=0°C)
1200
---
--- V(rms)
Receiver Input Voltage
0 --- 2.4 V
Differential Input High Threshold(VTH)*1
---
--- VOS+0.1
V
Differential Input Low Threshold(VTL)*1 VOS-0.1
---
---
V
Current Consumption *2 (IDD)
--- 200 --- mA
*3 (IFL)
2 6.0 6.0 mA(rms)
*2 *3 Power Consumption
--- 1.92 ---
W
--- 3.13 ---
W
--- 4.17 ---
W
*1 : Refer to DF90CF364 Specification by National Semiconductor Corporation.
*2 : 8 color bars pattern
*3 : Excepting the efficiency FL inverter
*4: Not use Hsync nor Vsync. Only ENAB control.
Remarks
IFL=6.0 mA(rms)
VOS:Offset Mode Voltage
VOS=+1.2V
IFL=2.0mA(rms) :VFL=615V(rms)
IFL=4.0mA(rms) :VFL=610V(rms)
IFL=6.0mA(rms) :VFL=580V(rms)
OPTICAL SPECIFICATION (Ta=25°C)
Item
Min. Typ. Max. Unit
Remarks
Contrast Ratio (CR)
100 250
---
---
Response Time
(tON)
--- 10 30 ms
Luminance (L)
(tOFF)
--- 20 40 ms
--- 50 --- cd/m2 IFL=2.0mA(rms) :VFL=615V(rms)
--- 110 --- cd/m2 IFL=4.0mA(rms) :VFL=610V(rms)
--- 150 --- cd/m2 IFL=6.0mA(rms) :VFL=580V(rms)
*The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
Toshiba or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Toshiba or others.
*The information contained herein may be changed without prior notice. It is therefore advisable to contact Toshiba before proceeding
with the design of equipment incorporating this product.
(1/10)
2001- 11-14 (Ver.2.4)
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
1 page  
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TIMING SPECIFICATION 1)2) 3) 4)
LTM12C324S
Signal
NCLK
HSYNC
VSYNC
Parameter
Clock Period
Frequency
High Time
Low Time
Setup to NCLK
Pulse Width
Pulse Width
VSYNC to DATA
Setup to HSYNC
Line Period
Symbol
ts
1/ts
tsh
tsl
tls
tlw
tfw
tfd
tfl
tlpd=tlpl
DATA
ENAB
Horizontal Display Time
Frame Frequency
Frame Period
Vertical Display Time
Setup
Hold
Setup
Hold
Display Start
thd
1/tfpd
tfpd=tfpf
tvd
tds
tdh
tdrs
tdrh
tdrds
Min.
15
-
6
7
7
8 x ts
3 x tlpd
7 x tlpd
16
1319 x ts
20.04
1024 x ts
58
778 x tlpd
768 x tlpd
5
7
10
10
-
Typ.
15.38
65
-
-
-
-
6 x tlpd
35 x tlpd
-
1344 x ts
20.68
1024 x ts
60
806 x tlpd
768 x tlpd
-
-
-
-
296 x ts
Max.
-
66.6
-
-
-
-
7 x tlpd
-
-
1462 x ts
22.16
1024 x ts
-
860 x tlpd
768 x tlpd
-
-
-
-
400 x ts
Unit
ns
MHz
ns
ns
ns
-
-
-
ns
-
μs
-
Hz
-
-
ns
ns
ns
ns
-
Remarks
5)
5)
5)
5)
5)
5)
5)
5)
Note 1) Refer to TIMING CHART and LVDS (DF90CF364MTD) specifications by National Semiconductor.
Note 2) If NCLK is fixed to "H" or "L" level for certain period, the panel may be damaged.
Note 3) Please adjust LCD operating signal timing and FL driving frequency, to optimize the display quality.
There is a possibility that flicker is observed by the interference of LCD operating signal timing and FL driving
Condition (especially driving frequency ), even if the condition satisfies above timing specifications and
recommended operating conditions shown in 3.
Notes 4) Do not hold NCLK on “H” level nor “L” level during VDD(+3.3V) Is supplied. When it holds on, DC voltage supplies
to liquid crystal materials and it may cause damage to liquid crystal materials.
Notes 5) These values are determined by the LCD module.
SEQUENCE OF POWER SUPPLIES AND SIGNALS
10ms(Max.)
10ms(Max.) 500ms(Min.)
3.0V
VDD 0.2V
40ms(Max.)
0ms(Min.)
CLK IN+
IN0+,IN1+,IN2+
10%
3.0V
40ms(Max.)
0ms(Min.)
0.2V
0.2V
10%
CLK IN-
IN0-,IN1-,IN2-
90%
90%
(5/10)
2001- 11-14 (Ver.2.4)
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
5 Page | ||
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