DataSheetWiki


GTLP16616MTD fiches techniques PDF

Fairchild Semiconductor - 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

Numéro de référence GTLP16616MTD
Description 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





1 Page

No Preview Available !





GTLP16616MTD fiche technique
June 1997
Revised October 1998
GTLP16616
17-Bit TTL/GTLP Bus Transceiver
with Buffered Clock
General Description
The GTLP16616 is a 17-bit registered bus transceiver that
provides TTL to GTLP signal level translation. It allows for
transparent, latched and clocked modes of data flow and
provides a buffered GTLP (CLKOUT) clock output from the
TTL CLKAB. The device provides a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP’s reduced output
swing (<1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver logic (GTL) JEDEC standard
JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic
levels
s Edge Rate Control to minimize noise on the GTLP port
s Power up/down/off high impedance for live insertion
s External VREF pin for receiver threshold
s CMOS technology for low power dissipation
s 5 V tolerant inputs and outputs on the A-Port
s Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs.
s TTL compatible driver and control inputs
s Flow through pinout optimizes PCB layout
s Open drain on GTLP to support wired-or connection
s A-port source/sink 32 mA/+32 mA
s D-type flip-flop, latch and transparent data paths
s GTLP Buffered CLKAB signal available (CLKOUT)
s Recommended Operating Temperature 40°C to 85°C
Ordering Code:
Order Number Package Number
Package Description
GTLP16616MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide
GTLP16616MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 1998 Fairchild Semiconductor Corporation DS500017.prf
www.fairchildsemi.com

PagesPages 10
Télécharger [ GTLP16616MTD ]


Fiche technique recommandé

No Description détaillée Fabricant
GTLP16616MTD 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock Fairchild Semiconductor
Fairchild Semiconductor

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche