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GTLP10B320MTD fiches techniques PDF

Fairchild Semiconductor - 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path

Numéro de référence GTLP10B320MTD
Description 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
Fabricant Fairchild Semiconductor 
Logo Fairchild Semiconductor 





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GTLP10B320MTD fiche technique
May 2001
Revised May 2001
GTLP10B320
10-Bit LVTTL/GTLP Transceiver
with Split LVTTL Port and Feedback Path
General Description
The GTLP10B320 is a 10-bit Universal bus driver and
receiver, with separate LVTTL inputs and outputs and a
feedback path for diagnostics, that provides LVTTL to
GTLP signal level translation. High speed backplane oper-
ation is a direct result of GTLP’s reduced output swing
(<1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the
Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output low level is typ-
ically less than 0.5V, the output level high is 1.5V and the
receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and LVTTL logic
levels
s Variable edge rate control pin to select desired edge rate
on GTLP port (VERC)
s VREF pin provides external supply reference voltage for
receiver threshold adjustibility
s Split LVTTL inputs and outputs
s Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s A feedback path for control and diagnostics monitoring
s TTL compatible driver and control inputs
s Designed using Fairchild advanced BiCMOS technology
s Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s Power up/down and power off high impedance for live
insertion
s Open drain on GTLP to support wired-or connection
s Flow through pinout optimizes PCB layout
s A Port source/sink 24mA/+24mA
s B Port sink +50mA
Ordering Code:
Order Number Package Number
Package Description
GTLP10B320MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500483
www.fairchildsemi.com

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