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PDF P645HW04-V0 Data sheet ( Hoja de datos )
| Número de pieza | P645HW04-V0 | |
| Descripción | Full HD Color TFT-LCD Module | |
| Fabricantes | AUO | |
| Logotipo |  |
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Model Name:P645HW04 V0
Product Specification
Rev.04
Date: 2011/1/7
Product Functional Specification
65" Full HD Color TFT-LCD Module
Model Name: P645HW04 V0
() Preliminary Specification
(*) Final Specification
©Copyright AU Optronics Corp.
R e v. 0 4
Page 2/32
2008 All Rights Reserved
No Reproduction and Redistribution Allowed
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Model Name:P645HW04 V0
Product Specification
2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit:
Item
Logic/LCD Drive Voltage
Input Voltage of Signal
BLU Input Voltage
BLU Brightness Control Voltage
Operating Temperature
Operating Humidity
Storage Temperature
Storage Humidity
Panel Surface Temperature
Symbol
VCC
VIN
VDDB
VBLON
TOP
HOP
TST
HST
TSUR
Min.
-0.3
-0.3
-0.3
-0.3
0
10
-20
10
--
Max
+14.0
+3.6
+27.0
+7.0
+50
90
+60
90
+65
Unit
V
V
V
V
°C
%RH
°C
%RH
°C
Note
[1]
[1]
[1]
[1]
[2]
[2]
[2]
[2]
[2]
Note [1]: If operate over spec but under absolute maximum rating, duration must be < 50ms.
Note [2]: Maximum Wet-Bulb should be 39°C and no condensation. The relative humidity must not
exceed 80% non-condensing at temperatures of 40°C or less. At temperatures greater than
40°C, the wet bulb temperature must not exceed 39°C. When operate at low temperatures,
the brightness of CCFL will drop and the life time of CCFL will be reduced.
©Copyright AU Optronics Corp.
R e v. 0 4
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2008 All Rights Reserved
No Reproduction and Redistribution Allowed
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Model Name:P645HW04 V0
Product Specification
3.3 Signal Timing Specification
This is the signal timing required at the input of the user connector. All of the interface signal timing should be
satisfied with the following specifications for its proper operation.
Timing Table (DE only Mode)
Signal
Item
Symbol
Min. Typ. Max Unit
Vertical Section
Period
Active
Tv
Tdisp (v)
1090ʳ
1125ʳ
1080
1480ʳ
Th
Th
Horizontal Section
Blanking
Period
Active
Tblk (v)
Th
Tdisp (h)
10ʳ
1030ʳ
45ʳ
1100ʳ
960
400ʳ
1325ʳ
Th
Tclk
Tclk
Clock
Blanking
Frequency
Tblk (h)
Fclk=1/Tclk
70ʳ
140ʳ
365ʳ
Tclk
50ʳ 74.25ʳ 82ʳ MHz
Vertical Frequency
Frequency
Fv
47ʳ 60ʳ 63ʳ Hz
Horizontal Frequency
Frequency
Fh
60ʳ 67.5ʳ 73ʳ KHz
Notes:
(1) Display position is specific by the rise of DE signal only.
Horizontal display position is specified by the rising edge of 1st DCLK after the rise of 1st DE, is displayed on the
left edge of the screen.
(2)Vertical display position is specified by the rise of DE after a “Low” level period equivalent to eight times of
horizontal period. The 1st data corresponding to one horizontal line after the rise of 1st DE is displayed at the top
line of screen.
(3)If a period of DE “High” is less than 1920 DCLK or less than 1080 lines, the rest of the screen displays black.
(4)The display position does not fit to the screen if a period of DE “High” and the effective data period do not
synchronize with each other.
©Copyright AU Optronics Corp.
R e v. 0 4
Page 12/32
2008 All Rights Reserved
No Reproduction and Redistribution Allowed
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
11 Page | ||
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| PDF Descargar | [ Datasheet P645HW04-V0.PDF ] | |
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