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GS9010ACTC Datasheet دیتاشیت PDF دانلود

دیتاشیت - ETC - Serial Digital Automatic Tuning Subsystem

شماره قطعه GS9010ACTC
شرح مفصل Serial Digital Automatic Tuning Subsystem
تولید کننده ETC 
آرم ETC 


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GS9010ACTC شرح
GENLINXGS9010A Serial Digital
Automatic Tuning Subsystem
FEATURES
when used with the GS9005A or GS9015A and the
GS9000B or GS9000S, the GS9010A:
- constitutes an automatic 'tweakless' Serial
Digital receiving system
- eliminates the need for trim pots and external
temperature compensation for bit rates to 370 Mb/s
- automatically determines whether data is 4ƒsc
or 4:2:2, and whether the 4ƒsc data is NTSC or
PAL
- acquires lock from a 'no signal' condition in typically
50 ms
- holds lock during data interruptions for typically 2s
- relocks from synchronous switching in less than
10 µs
16 pin SOIC packaging
operates from a single +5 or -5 volt supply
typically consumes only 40 mW
immunity to spurious HSYNC inputs
defines minimum GS9005A VCO frequency after
extended absence of input signal
matches GS9005A capture range
APPLICATIONS
• 4ƒsc, 4:2:2 & 360 Mb/s serial digital interfaces
ORDERING INFORMATION
Part Number
Package Type
Temperature Range
GS9010ACKC 16 Pin Wide SOIC
0° to 70° C
GS9010ACTC 16 Pin Wide SOIC Tape
0° to 70° C
DEVICE DESCRIPTION
DATA SHEET
The GENLINXGS9010A is a monolithic integrated
circuit designed to be an Automatic Tuning Subsystem
(ATS) when used with the GS9005A Receiver or the
GS9015A Reclocker and the GS9000B or GS9000S Decoder.
The GS9010A ATS eliminates the need to manually set or
externally temperature compensate the Receiver or Reclocker
VCO. The GS9010A can also determine whether the
incoming data stream is 4ƒsc NTSC, 4ƒsc PAL or component
4:2:2.
The GS9010A is an enhanced version of the GS9010. Pin
compatible with the GS9010, the GS9010A offers improved
noise immunity to spurious HSYNC signals.
The GS9010A includes a ramp generator/oscillator which
repeatedly sweeps the Receiver/Reclocker VCO frequency
over a set range until the system is correctly locked. Once
locked, an automatic fine tuning (AFT) loop maintains the
VCO control voltage at its optimum centre point over
variations in temperature. During normal operation, the
GS9000B or GS9000S Decoder provides continuous HSYNC
pulses which disable the ramp/oscillator of the GS9010A.
This maintains the correct Receiver/Reclocker VCO
frequency. When an interruption to the incoming data
stream is detected by the Receiver/Reclocker, the Carrier
Detect goes LOW and opens the AFT loop in order to
maintain the correct VCO frequency for a period of typically
2 seconds. If the signal is re-established within this 2
seconds, the Receiver/Reclocker will rapidly relock. For
periods longer than typically 2 seconds, the VCO slowly
drifts towards a minimum frequency. Typically after 2
minutes, the serial clock output of the PLL settles to
approximately 85 MHz when ƒ/2 is high or 170 MHz
when ƒ/2 is low. The GS9010A is packaged in a 16 pin
wide SOIC, operates from a single +5 or -5 volt supply
and typically consumes 40 mW of power.
PAL/NTSC
FREQUENCY
COMPENSATION
1
4
LOOP FILTER
(from GS9005A)
5
CARRIER DETECT
(from GS9005A) 14
18k
11
OSCILLATOR
ƒ/2 6
(to GS9005A)
DELAY 10
÷4
VREF
20k
+
-
+
-
OSCILLATOR
COMPOSITE /
COMPONENT
DETECTOR
16 STANDARDS
THRESHOLD ADJUST
2 OUT
(to GS9005A)
3
IN-
13 HSYNC
( (from GS9000B
o orGS9000S)
25k8
SWF
(from GS9000B
or GS9000S)
9
FV CAP
Revision Date: August 1997
FUNCTIONAL BLOCK DIAGRAM
Document No. 521 - 01 - 05
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan Corporation: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan tel. (03) 3334-7700 fax (03) 3247-8839

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