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PDF AD9785 Data sheet ( Hoja de datos )
| Número de pieza | AD9785 | |
| Descripción | Dual 12-/14-/16-Bit 800 MSPS DAC | |
| Fabricantes | Analog Devices | |
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Data Sheet
Dual 12-/14-/16-Bit 800 MSPS DAC
with Low Power 32-Bit Complex NCO
AD9785/AD9787/AD9788
FEATURES
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Low power, fine complex NCO allows carrier placement
anywhere in DAC bandwidth while adding <300 mW power
Auxiliary DACs allow I and Q gain matching and offset control
Includes programmable I and Q phase compensation
Internal digital upconversion capability
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed pad TQFP package
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM
Digital high or low IF synthesis
Transmit diversity
Wideband communications
LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9785/AD9787/AD9788 are 12-bit, 14-bit, and 16-bit,
high dynamic range TxDAC® devices, respectively, that provide
a sample rate of 800 MSPS, permitting multicarrier generation
up to the Nyquist frequency. Features are included for optimizing
direct conversion transmit applications, including complex
digital modulation, as well as gain, phase, and offset compens-
ation. The DAC outputs are optimized to interface seamlessly
with analog quadrature modulators, such as the ADL5375
family from Analog Devices, Inc. A serial peripheral interface
(SPI) provides for programming and readback of many internal
parameters. Full-scale output current can be programmed over
a range of 10 mA to 30 mA. The AD9785/AD9787/AD9788
family is manufactured on a 0.18 μm CMOS process and operates
from 1.8 V and 3.3 V supplies. It is enclosed in a 100-lead TQFP
package.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals from baseband
to high intermediate frequencies.
2. Proprietary DAC output switching technique enhances
dynamic performance.
3. CMOS data input interface with adjustable setup and hold.
4. Low power complex 32-bit numerically controlled
oscillators (NCOs).
COMPLEX I AND Q
DC
FPGA/ASIC/DSP
TYPICAL SIGNAL CHAIN
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
DC
LO
DIGITAL INTERPOLATION FILTERS
I DAC
Q DAC
POST DAC
ANALOG FILTER
A
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9785/AD9787/AD9788
Parameter
LATENCY (DACCLK CYCLES)
1× Interpolation
2× Interpolation
4× Interpolation
8× Interpolation
Inverse Sinc
POWER-UP TIME2
DAC Wake-Up Time3
DAC Sleep Time4
Test Conditions/Comments
With or without modulation
With or without modulation
With or without modulation
With or without modulation
IOUT current settling to 1%
IOUT current to less than 1% of full scale
1 Timing vs. temperature and data valid windows are delineated in Table 25.
2 Measured from SPI_CS rising edge on Register 0x00; toggle Bit 4 from 0 to 1. VREF decoupling capacitor = 0.1 µF.
3 Measured from SPI_CS rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 0 to 1.
4 Measured from SPI_CS rising edge on Register 0x05 or Register 0x07; toggle Bit 15 or Bit 14 from 1 to 0.
Min Typ Max Unit
40 Cycles
83 Cycles
155 Cycles
294 Cycles
18 Cycles
260 ms
22 ms
22 ms
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 3.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (IN-BAND SFDR)
fDACCLK = 200 MSPS, fOUT = 70 MHz 1× Interpolation
fDACCLK = 200 MSPS, fOUT = 70 MHz 2× Interpolation
fDACCLK = 200 MSPS, fOUT = 70 MHz 4× Interpolation
fDACCLK = 800 MSPS, fOUT = 40 MHz 8× Interpolation
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDATA = 200 MSPS, fOUT = 50 MHz 1× Interpolation
fDATA = 200 MSPS, fOUT = 50 MHz 2× Interpolation
fDATA = 200 MSPS, fOUT = 100 MHz 4× Interpolation
fDATA = 100 MSPS, fOUT = 100 MHz 8× Interpolation
NOISE SPECTRAL DENSITY (NSD), EIGHT TONE, 500 kHz TONE
SPACING
fDACCLK = 200 MSPS, fOUT = 80 MHz
fDACCLK = 400 MSPS, fOUT = 80 MHz
fDACCLK = 800 MSPS, fOUT = 80 MHz
WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDACCLK = 491.52 MSPS, fOUT = 100 MHz 4× Interpolation
fDACCLK = 491.52 MSPS, fOUT = 200 MHz 4× Interpolation
WCDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO
(ACLR), SINGLE CARRIER
fDACCLK = 491.52 MSPS, fOUT = 100 MHz 4× Interpolation
fDACCLK = 491.52 MSPS, fOUT = 200 MHz 4× Interpolation
AD9785
AD9787
AD9788
Min Typ Max Min Typ Max Min Typ Max Unit
80 82 83 dBc
80 82 83 dBc
78 80 81 dBc
85 87 90 dBc
80 82 83 dBc
78 79 80 dBc
78 79 80 dBc
70 70 70 dBc
−154
−154
−154
−157
−158
−159
−158
−161
−162
dBm/Hz
dBm/Hz
dBm/Hz
78 80 82 dBc
72 74 76 dBc
80 82 88 dBc
78 80 82 dBc
Rev. B | Page 5 of 64
5 Page 
Data Sheet
AD9785/AD9787/AD9788
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
CVDD18 1
CVDD18 2
CGND 3
CGND 4
REFCLK+ 5
REFCLK– 6
CGND 7
CGND 8
CVDD18 9
CVDD18 10
CGND 11
AGND 12
SYNC_I+ 13
SYNC_I– 14
DGND 15
DVDD18 16
P1D[15] 17
P1D[14] 18
P1D[13] 19
P1D[12] 20
P1D[11] 21
DGND 22
DVDD18 23
P1D[10] 24
P1D[9] 25
PIN 1 INDICATOR
ANALOG DOMAIN
DIGITAL DOMAIN
AD9788
TOP VIEW
(Not to Scale)
75 I120
74 VREF
73 IPTAT
72 AGND
71 IRQ
70 RESET
69 SPI_CS
68 SCLK
67 SPI_SDIO
66 SPI_SDO
65 PLL_LOCK
64 DGND
63 SYNC_O+
62 SYNC_O–
61 DVDD33
60 DVDD18
59 P2D[0]
58 P2D[1]
57 P2D[2]
56 P2D[3]
55 P2D[4]
54 DGND
53 DVDD18
52 P2D[5]
51 P2D[6]
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTES
1. THE EPAD IS A CONDUCTIVE HEAT SINK. CONNECT THE EPAD TO ANALOG COMMON (AGND).
Figure 4. AD9788 Pin Configuration
Table 8. AD9788 Pin Function Descriptions
Pin No.
Mnemonic Description
1, 2, 9, 10
3, 4, 7, 8, 11
CVDD18
CGND
1.8 V Clock Supply.
Clock Common.
5 REFCLK+ Differential Clock Input, Positive.
6 REFCLK− Differential Clock Input, Negative.
12, 72, 77, 79, 81, 82, 85, AGND
88, 91, 94, 95, 97, 99
Analog Common.
13
14
15, 22, 32, 44, 54, 64
SYNC_I+
SYNC_I−
DGND
Differential Synchronization Input, Positive.
Differential Synchronization Input, Negative.
Digital Common.
16, 23, 33, 43, 53, 60
DVDD18 1.8 V Digital Supply.
17
P1D[15]
Port 1, Data Input D15 (MSB).
18
P1D[14]
Port 1, Data Input D14.
19
P1D[13]
Port 1, Data Input D13.
20
P1D[12]
Port 1, Data Input D12.
21
P1D[11]
Port 1, Data Input D11.
24
P1D[10]
Port 1, Data Input D10.
25
P1D[9]
Port 1, Data Input D9.
26
P1D[8]
Port 1, Data Input D8.
27
P1D[7]
Port 1, Data Input D7.
28
P1D[6]
Port 1, Data Input D6.
29
P1D[5]
Port 1, Data Input D5.
Rev. B | Page 11 of 64
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9785.PDF ] | |
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