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PDF AA084SB01-T2 Data sheet ( Hoja de datos )
| Número de pieza | AA084SB01-T2 | |
| Descripción | SVGA Display Module | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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TENTATIVE
All information in this technical data sheet is tentative
and subject to change without notice.
Preliminary
8.4” SVGA
TECHNICAL SPECIFICATION
AA084SB01--T2
MITSUBISHI ELECTRIC Corp.
MITSUBISHI Confidential
(1/29)
Date: Sept.4,’09
AA084SB01--T2_02_00
1 page  
3. ABSOLUTE MAXIMUM RATINGS
ITEM
SYMBOL
MIN.
MAX.
UNIT
Power Supply Voltage for LCD
VCC 0 4.0 V
Logic Input Voltage
VI −0.3 VCC+0.3 V
Backlight (LED) Current
IF 0 180 mA
Touch Panel Voltage
TPV -- 7.0 V
Operation Temperature (Touch Panel) Note 1,2) Top(TouchPanel)
−20
70 °C
Operation Temperature (Ambient) Note 2)
Top(Ambient)
−20
70 °C
Storage Temperature
Note 2)
Tstg
−20
80 °C
[Note]
1) Measured at the center of active area and at the center of panel back surface
2) Top,Tstg ≤ 40°C : 90%RH max. without condensation
Top,Tstg > 40°C : Absolute humidity shall be less than the value of 90%RH at 40°C without
condensation.
4. ELECTRICAL CHARACTERISTICS
(1) TFT- LCD
ITEM
SYMBOL MIN.
Power Supply Voltage for LCD
VCC
3.0
Power Supply Current for LCD
ICC
--
Permissive Input Ripple Voltage VRP
--
Logic Input Voltage
High
Low
VIH
VIL
2.4
0
TYP.
3.3
350
--
--
--
Ambient Temperature : Ta = 25°C
MAX. UNIT
Remarks
3.6 V
*1)
540 mA
*2)
100 mVp-p VCC = +3.3 V
VCC V MODE, SC
0.8 V MODE, SC
*1) Power and signals sequence:
t1 ≤ 10 ms
0 < t2 ≤ 50 ms
0 < t3 ≤ 50 ms
200 ms ≤ t4
200 ms ≤ t5
0 ≤ t6
LCD Power Supply
0.9VCC
Logic Signal
0.1VCC
VCC
data
0.9VCC
0.1VCC 0.1VCC
t1 t2
t3 t4
Backlight Power Supply
t5 t6
data: RGB DATA, DCLK, DENA, MODE, SC
MITSUBISHI Confidential
(5/29)
AA084SB01--T2_02_00
5 Page 
6. INTERFACE TIMING
LVDS transmitter input signal
(1) Timing Specifications
ITEM
SYMBOL MIN
TYP
MAX
UNIT
DCLK
Frequency
Period
fCLK
tCLK
35
23.8
40 42 MHz
25 28.6
ns
Active Time
tHA 800 800 800 tCLK
Blanking Time
Horizontal
Frequency
tHB
fH
20
35.2
256 --
37.9 39.2
tCLK
kHz
DENA
Period
Active Time
tH 25.5 26.4 28.4
tVA 600 600 600
μs
tH
Vertical
Blanking Time
Frequency
tVB
fV
3
55
28 --
60 64.2
tH
Hz
Period
tV 15.6 16.7 18.2 ms
[Note]
1) DENA (Data Enable) should always be positive polarity as shown in the timing specification.
2) DCLK should appear during all invalid period.
3) LVDS timing follows the timing specifications of LVDS receiver IC: THC63LVDF84B(Thine).
4) In case of blanking time fluctuation, please satisfy following condition.
tVBn > tVBn-1 − 3(tH)
MITSUBISHI Confidential
(11/29)
AA084SB01--T2_02_00
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AA084SB01-T2.PDF ] | |
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