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PDF HC6094IN Data sheet ( Hoja de datos )

Número de pieza HC6094IN
Descripción ADSL Analog Front End Chip
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! HC6094IN Hoja de datos, Descripción, Manual

[ /Title
(HC60
94)
/Sub-
ject
(ADSL
Ana-
log
Front
End
Chip)
/Autho
r ()
/Key-
words
(Har-
ris
Semi-
con-
ductor,
Tele-
com,
SLICs,
SLACs
, Tele-
phone,
Tele-
phony,
WLL,
Wire-
less
Local
Loop,
PBX,
Pri-
vate
Branch
Exchan
ge,
NT1+,
CO,
Cen-
Semiconductor
February 1999
NO
Call
CRoeErnOCetrOBmaSMlaOAiMl:pLEpEcNlTeiDcnEaEtaPtDipoRpRnO@sEDP1hUL-aC8Ar0rTCi0sE-.4cM4o2Em-N7T747
HC6094
ADSL Analog Front End Chip
Features
• 14-Bit 5 MSPS DAC
• Programmable Gain Stages
• Anti-Aliasing and Reconstruction Filters
Applications
• FDM DMT ADSL
• CAP ADSL
• EC DMT ADSL
• Communications Receiver
Description
The HC6094 performs the Analog processing for the ADSL
chip set. The transmit chain has a 14 Bit DAC, a third-order
Chebyshev reconstruction filter and a programmable attenu-
ator (-12 to 0dB) capable of driving a 220differential load.
The receiver chain has a high impedance input stage, pro-
grammable gain stage (0 to 24dB), additional programmable
gain (-9 to 18dB) and a third-order Chebyshev anti-aliasing
filter for driving an off-chip A/D.
Laser trimmable thin-film resistors are used to set the filter
cutoff frequency and DAC linearity. The transmit and receive
signal chains are specified at 65dB MTPR.
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)
PACKAGE
HC6094IN
-40 to 85 44 Ld MQFP
PKG. NO.
Q44.10x10
Pinout
HC6094
(MQFP)
TOP VIEW
44 43 42 41 40 39 38 37 36 35 34
D11 1
33 VSSA_ATT
D10 2
32 VDDA_TX
D9 3
31 VSSA_TX
D8 4
30 ARTN
D7 5
29 VDDD_RX
D6 6
28 CS
D5 7
27 SDI
D4 8
26 RST
D3 9
25 SCLK
D2 10
24 GNDD__RX
D1
11 23
12 13 14 15 16 17 18 19 20 21 22
GNDA_RX
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1999
1
File Number 4260.2

1 page




HC6094IN pdf
HC6094
Definitions
1. Supply currents/power dissipation measured in a quiescent (static) state with RL open.
2. Logic input levels and timing are verified by using them as conditions for testing DAC and filter.
3. Digital input currents are measured at 0V and VCC.
4. DAC resolution and monotonicity guaranteed by ILE and DLE tests.
5. DAC ILE is relative to best fit straight line.
6. Output drive current is the output current at 0V for each output when they are driven to ± Full Scale.
7. Output offset measured with VIN = 0V differential for the RX, and the DAC at mid scale for the TX.
8. PSRR is the change in differential input voltage vs. change in supply voltage at DC.
9. TX Gain is calculated as 20*Log((TXoutDACFS - TXoutDACZS)/12V) at DC.
10. RX input swing is verified by using this as condition for gain testing.
11. RX Input Impedance is calculated as VIN/IIN where VIN is the maximum input voltages, with the PGA set to 0dB.
12. RX CMRR is calculated as 20*Log(VOUT/VIN)-PGA Gain. VIN is set to 250mVPEAK (CMIR) at 1.1MHz, and PGA gain is
set to maximum.
13. RX Gain is calculated as 20*Log(dVOUT/dVIN), where VIN is set to give a nominal ± Output Swing, or the maximum input
swing, whichever is smaller. It is tested DC.
14. Filter Gain/Attenuation is relative to low frequency passband gain. TX tested by driving the DAC (with sinX/X correction),
RX tested by driving PGA2. Wafer probe will use special test points to bypass the DAC for laser trimming.
15. MTPR - (Multi-Tone Power Ratio). A DMT waveform is generated which has a specific crest factor or peak to average ratio
(PAR) with specific carriers missing. The waveform is then passed through the TX or RX chain. The total integrated power
of the notch at the location of the missing carriers is measured with respect to the adjacent carriers. Notch depth is mea-
sured for several DMT waveforms with different PARs. The notch depths for each DMT waveform are averaged to give an
MTPR number.
5

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