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PDF QX82527 Data sheet ( Hoja de datos )
| Número de pieza | QX82527 | |
| Descripción | SERIAL COMMUNICATIONS CONTROLLER | |
| Fabricantes | Intel | |
| Logotipo |  |
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82527
SERIAL COMMUNICATIONS CONTROLLER
CONTROLLER AREA NETWORK PROTOCOL
Automotive
Y Supports CAN Specification 2 0
Standard Data and Remote Frames
Extended Data and Remote Frames
Y Programmable Global Mask
Standard Message ldentifier
Extended Message ldentifier
Y 15 Message Objects of 8-Byte Data
Length
14 Tx Rx Buffers
1 Rx Buffer with Programmable Mask
Y Flexible CPU Interface
8-Bit Multiplexed
16-Bit Multiplexed
8-Bit Non-Multiplexed
(Synchronous Asynchronous)
Serial Interface
Y Programmable Bit Rate
Y Programmable Clock Output
Y Flexible Interrupt Structure
Y Flexible Status Interface
Y Configurable Output Driver
Y Configurable Input Comparator
Y Two 8-Bit Bidirectional I O Ports
Y 44-Lead PLCC Package
Y 44-Lead QFP Package
Y Pinout Compatibility with the 82526
The 82527 serial communications controller is a highly integrated device that performs serial communication
according to the CAN protocol It performs all serial communication functions such as transmission and
reception of messages message filtering transmit search and interrupt search with minimal interaction from
the host microcontroller or CPU
The 82527 is Intel’s first device to support the standard and extended message frames in CAN Specification
2 0 Part B It has the capability to transmit receive and perform message filtering on extended message
frames Due to the backwardly compatible nature of CAN Specification 2 0 the 82527 also fully supports the
standard message frames in CAN Specification 2 0 Part A
The 82527 features a powerful CPU interface that offers flexibility to directly interface to many different CPUs
It can be configured to interface with CPUs using an 8-bit multiplexed 16-bit multiplexed or 8-bit non-multi-
plexed address data bus for Intel and non-Intel architectures A flexible serial interface (SPI) is also available
when a parallel CPU interface is not required
The 82527 provides storage for 15 message objects of 8-byte data length Each message object can be
configured as either transmit or receive except for the last message object The last message object is a
receive-only buffer with a special mask design to allow select groups of different message identifiers to be
received
The 82527 also implements a global masking feature for message filtering This feature allows the user to
globally mask any identifier bits of the incoming message The programmable global mask can be used for
both standard and extended messages
The 82527 PLCC offers hardware or pinout compatibility with the 82526 It is pin-to-pin compatible with the
82526 except for pins 9 30 and 44 These pins are used as chip selects on the 82526 and are used as CPU
interface mode selection pins on the 82527
The 82527 is fabricated using Intel’s reliable CHMOS III 5V technology and is available in either 44-lead PLCC
or 44-lead QFP for the automotive temperature range (b40 C to a125 C)
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
December 1995
Order Number 272250-006
1 page  
82527
Pin Name
AD0 A0 ICP
AD1 A1 CP
AD2 A2 CSAS
AD3 A3 STE
AD4 A4 MOSI
AD5 A5
AD6 A6 SCLK
AD7 A7
AD8 D0 P1 0
AD9 D1 P1 1
AD10 D2 P1 2
AD11 D3 P1 3
AD12 D4 P1 4
AD13 D5 P1 5
AD14 D6 P1 6
AD15 D7 P1 7
P2 0
P2 1
P2 2
P2 3
P2 4
P2 5
P2 6 INT
P2 7 WRH
Mode0
Mode1
ALE AS
RD
E
WR WRL
RW
READY
MISO
DSACK0
Pin Type
I O-I-I
I O-I-I
I O-I-I
I O-I
I O-I-I
I O-I
I O-I-I
I O-I
I O-O-I O
I O-O-I O
I O-O-I O
I O-O-I O
I O-O-I O
I O-O-I O
I O-O-I O
I O-O-I O
IO
IO
IO
IO
IO
IO
I O-O
I O-I
I
I
I-I
I
I
I
I
O
O
O
Pin Description
Address Data bus in 8-bit multiplexed mode
Address bus in 8-bit non-multiplexed mode
Low byte of A D bus in 16-bit multiplexed mode
In Serial Interface mode the following pins have the following meaning
AD0 ICP
Idle Clock Polarity
AD1 CP
Clock Phase
AD2 CSAS Chip Select Active State
AD3 STE Sync Transmit Enable
AD6 SCLK Serial Clock Input
AD4 MOSI Serial Data Input
High byte of A D bus in 16-bit multiplexed mode
Data bus in 8-bit non-multiplexed mode
Low speed I O port P1 pins in 8-bit multiplexed mode and serial mode
Port pins have weak pullups until the port is configured by writing to 9FH
and AFH
P2 in all modes
P2 6 is INT when MUX e 1 and is open-drain
P2 7 is WRH in 16-bit multiplexed mode
These pins select one of the four parallel interfaces These pins are
weakly held low during reset
Mode1 Mode0
0 0 8-bit multiplexed Intel
0 0 Serial Interface mode entered when RD e 0
WR e 0 upon reset
0 1 16-bit multiplexed Intel
1 0 8-bit multiplexed non-Intel
1 1 8-bit non-multiplexed
ALE used for Intel modes
AS used for non-Intel modes except Mode 3 this pin must be tied high
RD used for Intel modes
E used for non-Intel modes except Mode 3 Asynchronous this pin must
be tied high
WR in 8-bit Intel mode and WRL in 16-bit Intel mode
R W used for non-Intel modes
READY is an output to synchronize accesses from the host
microcontroller to the 82527 READY is an open-drain output to the host
microcontroller MISO is the serial data output for the serial interface
mode
DSACK0 is an open-drain output to synchronize accesses from the host
microcontroller to the 82527
5
5 Page 
82527
A C Characteristics for 8-Bit Multiplexed Non-Intel Mode (Mode 2)
Conditions VCC e 5V g10% VSS e 0V TA e b40 C to a125 C CL e 100 pF
Symbol
Parameter
Min
Max
1 tXTAL Oscillator Frequency
1 tSCLK System Clock Frequency
1 tMCLK Memory Clock Frequency
tAVSL Address Valid to AS Low
tSLAX Address Hold after AS Low
tELDZ Data Float after E Low
tEHDV E High to Data Valid for Registers 02H
04H 05H
8 MHz
4 MHz
2 MHz
7 5 ns
10 ns
0 ns
0 ns
16 MHz
10 MHz
8 MHz
45 ns
45 ns
for Read Cycle without a Previous Write(1)
for Read Cycle with a Previous Write
(for Registers except for 02H 04H 05H)
1 5 tMCLK a 100 ns
3 5 tMCLK a 100 ns
tQVEL
tELQX
tELDV
tEHEL
tELEL
Data Setup to E Low
Input Data Hold after E Low
E Low to Output Data Valid on Port 1 2
E High Time
End of Previous Write (Last E Low) to E
Low for a Write Cycle
30 ns
20 ns
tMCLK
45 ns
2 tMCLK
2 tMCLK a 500 ns
tSHSL
tRSEH
tSLEH
tCLSL
tELCH
tCOPD
tCHCL
AS High Time
Setup Time of R W to E High
AS Low to E High
CS Low to AS Low
E Low to CS High
CLKOUT Period
CLKOUT High Period
30 ns
30 ns
20 ns
20 ns
0 ns
(CDV a 1)
(CDV a 1) tOSC(3)
tOSC b 10 (CDV a 1)
tOSC a 15
NOTES
1 Definition of ‘‘Read Cycle without a Previous Write’’ The time between the falling edge of E (for the previous write cycle)
and the rising edge of E (for the current read cycle) is greater than 2 tMCLK
2 Definition of ‘‘Write Cycle with a Previous Write’’ The time between the falling edge of E (for the previous write cycle) and
the falling edge of E (for the current write cycle) is less than 2 tMCLK
3 Definition of CDV is the value loaded in the CLKOUT register representing the CLKOUT divisor
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet QX82527.PDF ] | |
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