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PDF ADP5135 Data sheet ( Hoja de datos )
| Número de pieza | ADP5135 | |
| Descripción | Triple 1800 mA Buck Regulators | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Triple 1800 mA Buck Regulators
With Precision Enables and Power Good Outputs
Preliminary Data Sheet
ADP5135
FEATURES
Main input voltage range: 3.0 V to 5.5 V
Three 1800 mA buck regulators
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±1.8%
Factory programmable or external adjustable VOUTx
Precision Enables for easier power sequencing
Power Good Pins for monitoring of each regulator
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2/BUCK3: output voltage range from 0.8 V to
3.8 V
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
Table 1. Family Models
Model Channels
Max Current Package
ADP5023 2 Bucks,1 LDO
ADP5024 2 Bucks,1 LDO
800mA, 300mA
1.2A, 300mA
ADP5034 2 Bucks,2 LDOs
1.2A, 300mA
ADP5037 2 Bucks,2 LDOs
800mA, 300mA
ADP5033
2 Bucks,2 LDOs with 2
EN pins
800mA, 300mA
ADP5040 1 Buck, 2 LDOs
1.2A, 300mA
ADP5041
1 Buck, 2 LDOs w/
Supevisory,
Watchdog, Manual
Reset
1.2A, 300mA
LFCSP (CP-24-10)
LFCSP (CP-24-10)
LFCSP (CP-24-10),
TSSOP (RE-28-1)
LFCSP (CP-24-10)
WLCSP (CB-16-8)
LFCSP (CP-20-10)
LFCSP (CP-20-10)
The ADP5135 combines three high performance buck
regulators. It is available in a 24-lead 4 mm × 4 mm LFCSP.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set to high, the buck regulators operate in
forced PWM mode. When the MODE pin is set to low, the buck
regulators operate in PWM mode only when the load is above a
predefined threshold. When the load current falls below this
predefined threshold, the regulator operates in power save
mode (PSM), improving the light load efficiency.
ADP5133 2 Bucks with 2 EN pins 800mA
WLFCSP (CB-16-8)
ADP5134
2 Bucks,2 LDOs w/ PE
and PG
1.2A, 300mA
LFCSP (CP-24-10)
Buck1 and Buck2 operate in sync and Buck3 operates out of
phase to reduce the input capacitor requirement.
Regulators in the ADP5135 are activated through dedicated
enable pins. The default output voltages can be externally set in
the adjustable version, or factory programmable to a wide range
of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT
Figure 1.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2014 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
AVIN to AGND
VIN1, VIN2, VIN3 to AVIN
PGND1, PGND2, PGND3 to AGND
VOUT1, VOUT2, VOUT3, FB1, FB2, FB3,
EN1, EN2, EN3, MODE, PG1, PG2, PG3
to AGND
SW1 to PGND1
SW2 to PGND2
SW3 to PGND3
Storage Temperature Range
Operating Junction Temperature
Range
Soldering Conditions
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to (AVIN + 0.3 V)
−0.3 V to (VIN1 + 0.3 V)
−0.3 V to (VIN2 + 0.3 V)
−0.3 V to (VIN3 + 0.3 V)
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
For detailed information on power dissipation, see the Power
Dissipation and Thermal Consideration section.
ADP5135
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
24-Lead, 0.5 mm pitch LFCSP
θJA θJC Unit
35 3 °C/W
ESD CAUTION
Rev. PrA | Page 5 of 25
5 Page 
Preliminary Data Sheet
ADP5135
Figure 21. Typical Waveforms, VOUT2 = 1.8V, Load current=50mA, Auto Mode
Figure 24. Typical Waveforms, VOUT2 = 1.8V, Load current=50mA, PWM Mode
Figure 22. Typical Waveforms, VOUT3 = 1.2V, Load current=50mA, Auto Mode
Figure 25. Typical Waveforms, VOUT3 = 1.2V, Load current=50mA, PWM Mode
Figure 23. Typical Waveforms, VOUT1 = 3.3V, Load current=50mA, PWM Mode
Figure 26. BUCK1 Response to Line Transient, Input Voltage from 4.5V to
5.5V, VOUT1 = 3.3V, Load current=50mA, PWM Mode
Rev. PrA | Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ADP5135.PDF ] | |
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