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PDF HC123 Data sheet ( Hoja de datos )
| Número de pieza | HC123 | |
| Descripción | Dual Retriggerable Monostable Multivibrator | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 1988
MM54HC123A MM74HC123A
Dual Retriggerable Monostable Multivibrator
General Description
The MM54 74HC123A high speed monostable multivibra-
tors (one shots) utilize advanced silicon-gate CMOS tech-
nology They feature speeds comparable to low power
Schottky TTL circuitry while retaining the low power and
high noise immunity characteristic of CMOS circuits
Each multivibrator features both a negative A and a posi-
tive B transition triggered input either of which can be
used as an inhibit input Also included is a clear input that
when taken low resets the one shot The ’HC123 can be
triggered on the positive transition of the clear while A is
held low and B is held high
The ’HC123A is retriggerable That is it may be triggered
repeatedly while their outputs are generating a pulse and
the pulse will be extended
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques The out-
Connection Diagram
Dual-In-Line Package
put pulse equation is simply PWe(REXT) (CEXT) where PW
is in seconds R is in ohms and C is in farads All inputs are
protected from damage due to static discharge by diodes to
VCC and ground
Features
Y Typical propagation delay 25 ns
Y Wide power supply range 2V – 6V
Y Low quiescent current 80 mA maximum (74HC Series)
Y Low input current 1 mA maximum
Y Fanout of 10 LS-TTL loads
Y Simple pulse width formula T e RC
Y Wide pulse range 400 ns to % (typ)
Y Part to part variation g5% (typ)
Y Schmitt Trigger A B inputs enable infinite signal input
rise and fall times
Timing Component
Note Pin 6 and Pin 14 must be
hard-wired to GND
TL F 5206 – 2
TL F 5206 – 1
Top View
Order Number MM54HC123A or MM74HC123A
Truth Table
Inputs
Clear A
LX
XH
XX
HL
Hv
uL
B
X
X
L
u
H
H
Outputs
QQ
LH
LH
LH
H e High Level
L e Low Level
u e Transition from Low to High
v e Transition from High to Low
e One High Level Pulse
e One Low Level Pulse
X e Irrelevant
C1995 National Semiconductor Corporation TL F 5206
RRD-B30M105 Printed in U S A
1 page  
sistor REXT toward VCC When the voltage across CEXT
equals VREF2 comparator C2 changes state causing the
output latch to reset (Q goes low) while at the same time
disabling comparator C2 This ends the timing cycle with the
monostable in the quiescent state waiting for the next trig-
ger
A valid trigger is also recognized when trigger input B goes
from GND to VCC (while input A is at GND and input clear is
at VCC k ) The ’HC123A can also be triggered when clear
goes from GND to VCC (while A is at GND and B is at
VCC o )
It should be noted that in the quiescent state CEXT is fully
charged to VCC causing the current through resistor REXT to
be zero Both comparators are ‘‘off’’ with the total device
current due only to reverse junction leakages An added
feature of the ’HC123A is that the output latch is set via the in-
put trigger without regard to the capacitor voltage Thus prop-
agation delay from trigger to Q is independent of the value
of CEXT REXT or the duty cycle of the input waveform
RETRIGGER OPERATION
The ’HC123A is retriggered if a valid trigger occurs l fol-
lowed by another trigger m before the Q output has re-
turned to the quiescent (zero) state Any retrigger after the
timing node voltage at the R CEXT pin has begun to rise
from VREF1 but has not yet reached VREF2 will cause an
increase in output pulse width T When a valid retrigger is
initiated m the voltage at the R CEXT pin will again drop to
VREF1 before progressing along the RC charging curve
toward VCC The Q output will remain high until time T after
the last valid retrigger
Because the trigger-control circuit flip-flop resets shortly af-
ter CX has discharged to the reference voltage of the lower
reference circuit the minimum retrigger time trr is a function
of internal propagation delays and the discharge time of CX
trr
20
a
187
VCC b 0
7
a
565
a (0
VCC
256 VCC)
b07 2
CX
Another removal retrigger time occurs when a short clear
pulse is used Upon receipt of a clear the one shot must
charge the capacitor up to the upper trip point before the
one shot is ready to receive the next trigger This time is
dependent on the capacitor used and is approximately
trr
e
196
a
640
VCC b 0
7
a
522 a (0 3
(VCC b
VCC)
0 7)2
CX
ns
RESET OPERATION
These one shots may be reset during the generation of the
output pulse In the reset mode of operation an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to VCC by turning on transistor Q1 n When
the voltage on the capacitor reaches VREF2 the reset latch
will clear and then be ready to accept another pulse If the
clear input is held low any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will
not change Since the Q output is reset when an input low
level is detected on the Clear input the output pulse T can
be made significantly shorter than the minimum pulse width
specification
Typical Output Pulse Width vs
Timing Components
Typical Distribution of Output
Pulse Width Part to Part
Typical 1ms Pulse Width
Variation vs Supply
TL F 5206–7
Minimum REXT vs
Supply Voltage
TL F 5206 – 8
TL F 5206 – 9
Typical 1ms Pulse Width
Variation vs Temperature
TL F 5206 – 10
Note R and C are not subjected to temperature The C is polypropylene
5
TL F 5206 – 11
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet HC123.PDF ] | |
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