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PDF HMT325S6CFR8C Data sheet ( Hoja de datos )

Número de pieza HMT325S6CFR8C
Descripción 204pin DDR3 SDRAM SODIMM
Fabricantes Hynix Semiconductor 
Logotipo Hynix Semiconductor Logotipo



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No Preview Available ! HMT325S6CFR8C Hoja de datos, Descripción, Manual

204pin DDR3 SDRAM SODIMM
DDR3 SDRAM
Unbuffered SODIMMs
Based on 2Gb C-die
HMT325S6CFR8C
HMT351S6CFR8C
*Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev. 0.2 / Aug. 2011
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1 page




HMT325S6CFR8C pdf
Pin Descriptions
Pin Name
CK[1:0]
CK[1:0]
CKE[1:0]
RAS
CAS
Description
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Num
ber
2
2
2
1
1
WE Write Enable
1
S[1:0]
A[9:0],A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
ODT[1:0]
SCL
SDA
SA[1:0]
Chip Selects
Address Inputs
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
On Die Termination Inputs
Serial Presence Detect (SPD)
Clock Input
SPD Data Input/Output
SPD Address Inputs
2
14
1
1
3
2
1
1
2
Pin Name
DQ[63:0]
DM[7:0]
DQS[7:0]
DQS[7:0]
EVENT
TEST
RESET
Description
Num
ber
Data Input/Output
64
Data Masks
8
Data strobes
8
Data strobes, negative line
8
Temperature event pin
1
Logic Analyzer specific test pin (No
connect on SODIMM)
1
Reset Pin
1
VDD Core and I/O Power
18
VSS Ground
52
VREFDQ
VREFCA
VTT
VDDSPD
NC
Input/Output Reference
Termination Voltage
SPD Power
Reserved for future use
1
1
2
1
2
Total: 204
Rev. 0.2 / Aug. 2011
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HMT325S6CFR8C arduino
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
Parameter
VDD Voltage on VDD pin relative to Vss
VDDQ Voltage on VDDQ pin relative to Vss
VIN, VOUT Voltage on any pin relative to Vss
TSTG Storage Temperature
Notes:
Rating
- 0.4 V ~ 1.975 V
- 0.4 V ~ 1.975 V
- 0.4 V ~ 1.975 V
-55 to +100
Units
V
V
V
oC
Notes
1,
1,
1
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
TOPER
Notes:
Parameter
Normal Operating Temperature Range
Extended Temperature Range
Rating
0 to 85
85 to 95
Units
oC
oC
Notes
1,2
1,3
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Hynix DDR3 SDRAMs sup-
port Auto Self-Refresh and Extended Temperature Range and please refer to Hynix component datasheet
and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range.
Rev. 0.2 / Aug. 2011
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