PDF M2F2G64CB88BHN Data sheet ( Hoja de datos )

Número de pieza	M2F2G64CB88BHN
Descripción	Unbuffered DDR3 SDRAM DIMM
Fabricantes	Nanya
Logotipo
Hay una vista previa y un enlace de descarga de M2F2G64CB88BHN (archivo pdf) en la parte inferior de esta página. Total 27 Páginas
No Preview Available ! M2F2G64CB88B7N / M2F4G64CB8HB5N M2F2G64CB88BHN / M2F4G64CB8HB9N 2GB: 256M x 64 / 4GB: 512M x 64PC3-8500 / PC3-10600/PC-12800 Unbuffered DDR3 SDRAM DIMM Based on DDR3-1066/1333/1600 256Mx8 (2GB/4GB) SDRAM B-Die Features •Performance: Speed Sort PC3-8500 PC3-10600 PC3-12800 -BE -CG -DI Unit DIMM CAS Latency 7 9 11 fck – Clock Frequency 533 667 800 tck – Clock Cycle 1.875 1.5 1.25 fDQ – DQ Burst Frequency 1066 1333 1600 • 240-Pin Dual In-Line Memory Module (UDIMM) • 256Mx64 (2GB) / 512Mx64 (4GB) DDR3 Unbuffered DIMM based on 256Mx8 DDR3 SDRAM B-Die devices. • Intended for 533MHz/667MHz/800MHz applications • Inputs and outputs are SSTL-15 compatible • VDD = VDDQ = 1.5V ±0.075V • SDRAMs have 8 internal banks for concurrent operation • Differential clock inputs • Data is read or written on both clock edges • DRAM DLL aligns DQ and DQS transitions with clock transitions. • Address and control signals are fully synchronous to positive clock edge • Nominal and Dynamtic On-Die Termination support • Halogen free product MHz ns Mbps • Programmable Operation: - DIMM  Latency: 6,7,8,9,10,11 - Burst Type: Sequential or Interleave - Burst Length: BC4, BL8 - Operation: Burst Read and Write • Two different termination values (Rtt_Nom & Rtt_WR) • 15/10/1 (row/column/rank) Addressing for 2GB • 15/10/2 (row/column/rank) Addressing for 4GB • Extended operating temperature rage • Auto Self-Refresh option • Serial Presence Detect • Gold contacts • 2GB/4GB SDRAMs are in 78-ball BGA Package • RoHS compliance and Halogen free Description M2F2G64CB88B7N / M2F4G64CB8HB5N / M2F2G64CB88BHN / M2F4G64CB8HB9N are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as one rank of 256Mx64 (2GB) and two ranks of 512Mx64 (4GB) high-speed memory array. Modules use eight 256Mx8 (2GB) 78-ball BGA packaged devices and sixteen 256Mx8 (4GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All Elixir DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint. The DIMM is intended for use in applications operating of 533MHz/667MHz/800MHz clock speeds and achieves high-speed data transfer rates of 1066Mbps/1333Mbps/1600Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A14 (2GB/4GB) and I/O inputs BA0~BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. Ordering Information REV 1.1 10/2010 1 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. 1 page M2F2G64CB88B7N / M2F4G64CB8HB5N M2F2G64CB88BHN / M2F4G64CB8HB9N 2GB: 256M x 64 / 4GB: 512M x 64PC3-8500 / PC3-10600/PC-12800 Unbuffered DDR3 SDRAM DIMM Functional Block Diagram [2GB – 1 Rank, 256Mx8 DDR3 SDRAMs]   DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7  DQS D0  ZQ  DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7  DQS D1  ZQ  DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7  DQS D2  ZQ  DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7  DQS D3  ZQ  DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39  DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47  DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55  DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7  DQS  D4 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7  DQS  D5 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7  DQS  D6 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7  DQS  D7 ZQ SCL SA0 SA1 SCL A0 A1 A2 SPD WP CKE0, A[13:0], , , , ODT0, BA[2:0],  CK  DDR3 SDRAM DDR3 SDRAM REV 1.1 10/2010 SDA VTT VDD VDDSPD VDD/VDDQ VREFDQ VSS VREFCA BA0-BA2 A0-A13   CKE0  ODT0 CK0   SPD D0-D7 D0-D7 D0-D7 D0-D7 BA0-BA2: SDRAMs D0-D7 A0-A13: SDRAMs D0-D7 : SDRAMs D0-D7 : SDRAMs D0-D7 CKE: SDRAMs D0-D7 : SDRAMs D0-D7 ODT: SDRAMs D0-D7 CK: SDRAMs D0-D7 : SDRAMs D0-D7 : SDRAMs D0-D7 Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown. 3. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ resistor is 240Ω±1%. 4. One SPD exists per module. 5 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. 5 Page M2F2G64CB88B7N / M2F4G64CB8HB5N M2F2G64CB88BHN / M2F4G64CB8HB9N 2GB: 256M x 64 / 4GB: 512M x 64PC3-8500 / PC3-10600/PC-12800 Unbuffered DDR3 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [2GB – 1 Rank, 256Mx8 DDR3 SDRAMs] Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 Parameter/Condition Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current PC3-8500 (-BE) 577 725 33 104 167 182 114 236 1011 1028 1531 83 2590 Operating, Standby, and Refresh Currents TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.5V ± 0.075V [4GB – 2 Ranks, 256Mx8 DDR3 SDRAMs] Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 Parameter/Condition Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current PC3-8500 (-BE) 813 961 66 209 333 364 228 472 1247 1264 1767 167 2826 PC3-10600 (-CG) 579 750 48 132 204 220 144 231 1302 1239 1507 56 2997 PC3-10600 (-CG) 810 980 95 264 408 440 289 461 1533 1470 1737 113 3228 PC3-12800 (-DI) 609 790 51 143 185 243 158 255 1510 1438 1531 56 3062 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA PC3-12800 (-DI) 864 1045 102 285 370 486 317 510 1765 1693 1786 113 3318 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA REV 1.1 10/2010 11 © NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. 11 Page

Páginas	Total 27 Páginas
PDF Descargar	[ Datasheet M2F2G64CB88BHN.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
M2F2G64CB88BHN	Unbuffered DDR3 SDRAM DIMM	Nanya

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar