PDF SEU02G64B4BF2SA-xxR Data sheet ( Hoja de datos )

Número de pieza	SEU02G64B4BF2SA-xxR
Descripción	SDRAM unbuffered DIMM
Fabricantes	Swissbit
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No Preview Available ! preliminary Data Sheet Rev.0.9 17.12.2012 2GB DDR2 – SDRAM unbuffered DIMM 240 Pin UDIMM SEU02G64B4BF2SA-xxR 2GByte in FBGA Technology RoHS compliant Options:  Data Rate / Latency DDR2 800 MT/s CL6 DDR2 667 MT/s CL5 Marking -25 -30  Module density 2048MB with 16 dies and 2 ranks  Standard Grade (TA) (TC) 0°C to 70°C 0°C to 85°C Environmental Requirements:  Operating temperature (ambient) Standard Grade 0°C to 70°C  Operating Humidity 10% to 90% relative humidity, noncondensing  Operating Pressure 105 to 69 kPa (up to 10000 ft.)  Storage Temperature -55°C to 100°C  Storage Humidity 5% to 95% relative humidity, noncondensing  Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C Features:  240-pin 64-bit Dual-In-Line Double Data Rate synchronous DRAM Module  Module organization: dual rank 256M x 64  VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V  1.8V I/O ( SSTL_18 compatible)  Auto Refresh (CBR) and Self Refresh 8k Refresh every 64ms  Serial Presence Detect with EEPROM  Gold-contact pads with 30µ” electrolytic gold  This module is fully pin and functional compatible to the JEDEC PC2-6400 spec. and JEDEC- Standard MO-237. (see www.jedec.org)  The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)]  DDR2 - SDRAM component SAMSUNG K4T1G084QF DIE Rev. F  128Mx8 DDR2 SDRAM in FBGA-60 package  4-bit prefetch architecture  DLL to align DQ and DQS transitions with CK  Multiple internal device banks for concurrent operation  Programmable CAS latency (CL)  Posted CAS additive latency (AL)  WRITE latency = READ latency – 1 tCK  Programmable burst length: 4 or 8  Adjustable data-output drive strength  On-die termination (ODT) Figure: mechanical dimensions1 Swissbit AG Industiestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 1if no tolerances specified ± 0.15mm www.swissbit.com eMail: [email protected] Page 1 of 16 1 page preliminary Data Sheet FUNCTIONAL BLOCK DIAGRAMM 2048MB DDR2 SDRAM DIMM, 2 RANKS AND 16 COMPONENTS Rev.0.9 17.12.2012 Swissbit AG Industiestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: [email protected] Page 5 of 16 5 Page preliminary Data Sheet Rev.0.9 17.12.2012 DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) (0°C ≤ TCASE ≤ + 85°C ; VDDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V) AC CHARACTERISTICS PARAMETER SYMBOL ODT power-down exit latency tAXPD ODT enable from MRS command tMOD Exit active power-down to READ tXARD command, MR [bit 12 = 0] Exit active power-down to READ tXARDS command, MR [bit 12 = 1] Exit precharge power-down to any non-READ command tXP CKE minimum high/low time tCKE 6400-6-6-6 MIN MAX 8- 12 - 2 8 – AL - - 2- 3- 5300-5-5-5 MIN MAX 8- 12 - 2- 7 - AL - 2- 3- Unit tCK ns tCK tCK tCK tCK Swissbit AG Industiestrasse 4 CH-9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: [email protected] Page 11 of 16 11 Page

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